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| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-09-07 19:02:05 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-09-22 21:02:03 +0200 |
| commit | 5ef337a0371e2b2c7905e7e20a38b6bfc80bb708 (patch) | |
| tree | 779823c3cff6633929662fa5ada75b773cffa7d9 /include/configs/imgtec_xilfpga.h | |
| parent | b838586086af3278bcaead3720c7a18813cf4619 (diff) | |
MIPS: cache: make index base address configurable
The index base address used for the cache initialisation is currently
hard-coded to CKSEG0. Make this value configurable if a MIPS system
needs to have a different address (e.g. in SRAM or ScratchPad RAM).
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'include/configs/imgtec_xilfpga.h')
0 files changed, 0 insertions, 0 deletions