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| author | Anthony Felice <tony.felice@timesys.com> | 2015-10-09 16:38:39 -0400 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-10-16 09:33:26 +0200 |
| commit | 42e550d44bc2335a18065b155cc408f30f0502ef (patch) | |
| tree | e11d8aab8ed9bf861b7cd9040717fbeb96c11a22 /include/configs/lsxl.h | |
| parent | f74dc51bcab924a30e41b33981a4f96af3f9dd57 (diff) | |
vf610twr: Fix typo in DRAM init
This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'include/configs/lsxl.h')
0 files changed, 0 insertions, 0 deletions