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authorPavel Kolesnikov <concord@emcraft.com>2007-07-20 15:03:03 +0200
committerStefan Roese <sr@denx.de>2007-07-20 15:03:03 +0200
commit531e3e8b831f357056448fa573137d5fb37000fd (patch)
treeb49334f81c18efb6fe8ced7f960e9075118e2253 /include/configs/lwmon5.h
parent8f085e324ad89423314b1a529a0dd5d85c8397ad (diff)
POST: Add ECC POST for the lwmon5 board
This patch adds ECC Post test for the Lwmon5 board based on PPC440EPx to U-Boot. Signed-off-by: Pavel Kolesnikov <concord@emcraft.com> Acked-by: Yuri Tikhonov <yur@emcraft.com> Acked-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/lwmon5.h')
-rw-r--r--include/configs/lwmon5.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index c4b7c4ee50..36ead23016 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -74,11 +74,13 @@
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
@@ -133,6 +135,10 @@
#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
#if 0 /* test-only: disable ECC for now */
#define CONFIG_DDR_ECC 1 /* enable ECC */
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_ECC)
+
#endif
/*-----------------------------------------------------------------------