diff options
| author | Parthiban Nallathambi <parthiban@linumiz.com> | 2020-07-27 16:48:41 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-08-03 17:03:57 +0200 |
| commit | 10e959a1ca85c66d877cc2fcab6e1fe49b478b1b (patch) | |
| tree | 7371867e3b6d434374e91e04540adfc7167fa427 /include/configs/mys_6ulx.h | |
| parent | ae28d33cdefec879c5dc44d7cad70d99279f67c2 (diff) | |
imx: Add MYiR Tech MYS-6ULX support
MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based
on imx6ULL SoC from NXP and provision for expansion board. This
commit adds support only for SBC with NAND.
CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C) at 45C
Reset cause: WDOG
Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND
Board: MYiR MYS-6ULX 6ULL Single Board Computer
DRAM: 256 MiB
NAND: 256 MiB
MMC: FSL_SDHC: 0
In: serial@2020000
Out: serial@2020000
Err: serial@2020000
Net: FEC0
Working:
- Eth0
- MMC/SD
- NAND
- UART 1
- USB host
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Diffstat (limited to 'include/configs/mys_6ulx.h')
| -rw-r--r-- | include/configs/mys_6ulx.h | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h new file mode 100644 index 0000000000..208779958f --- /dev/null +++ b/include/configs/mys_6ulx.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban@linumiz.com> + */ + +#ifndef __MYS_6ULX_H +#define __MYS_6ULX_H + +#include <linux/sizes.h> +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_IMX_THERMAL + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200n8\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#endif /* __MYS_6ULX_H */ |