diff options
| author | Wenyou Yang <wenyou.yang@microchip.com> | 2017-09-13 14:58:50 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-09-14 16:02:44 -0400 |
| commit | 23a19e03589c0b1c4daec082f33a1ecdbf5a4475 (patch) | |
| tree | ed8e76c277b06a93ea1eb708b6cd7288dc1c6e1b /include/configs/sama5d2_xplained.h | |
| parent | 2b21cf55cc767bc1303f22c3f6f7b9d6f0845c02 (diff) | |
board: sama5d2_xplained: Make SPL work on spiflash
Because before switching to a lower clock source, we must switch
the clock source first instead of last. So before configuring the
PMC_MCKR register, invoke at91_mck_init_down() first.
As said in datasheet, the the size of SPL must not exceed the maximum
size allowed(64Kbytes).
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/sama5d2_xplained.h')
| -rw-r--r-- | include/configs/sama5d2_xplained.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index 891218d83e..aedd5684c4 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -61,7 +61,7 @@ /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x18000 +#define CONFIG_SPL_MAX_SIZE 0x10000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |