diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-27 15:55:32 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:34 +0100 |
| commit | a76b711deab28ff6f9436908116c2506115916e5 (patch) | |
| tree | a4693f978bffabc34023bd3f7c5c41aceb98f590 /include/configs/socfpga_soc64_common.h | |
| parent | 380477f1d19b73e2bf7fe5199e45e0951ee6640e (diff) | |
arm: socfpga: agilex: Enable Agilex SoC build
Add build support for Agilex SoC.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'include/configs/socfpga_soc64_common.h')
| -rw-r--r-- | include/configs/socfpga_soc64_common.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index f69a55c191..4b27483788 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -87,7 +87,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=Image\0" \ "fdt_addr=8000000\0" \ - "fdtimage=socfpga_stratix10_socdk.dtb\0" \ + "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "mmcroot=/dev/mmcblk0p2\0" \ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ " root=${mmcroot} rw rootwait;" \ @@ -155,10 +155,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_HW_WATCHDOG #define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) #endif +#else +#define CONFIG_DW_WDT_CLOCK_KHZ 100000 +#endif #endif /* |