summaryrefslogtreecommitdiff
path: root/include/configs/strider.h
diff options
context:
space:
mode:
authorMario Six <mario.six@gdsys.cc>2019-01-21 09:18:01 +0100
committerMario Six <mario.six@gdsys.cc>2019-05-21 07:52:33 +0200
commita8f975391f2452bc7a51eeafd030c85c32e1aca5 (patch)
tree8b5bc02ac3891c277a8cae70dcf951f86c705f65 /include/configs/strider.h
parent87ee51048eae94eb5c075b6c900d4da5e9531cf4 (diff)
mpc83xx: Simplify BR,OR lines
Re-format all BR,OR #define lines into single lines. This makes them harder to read, but accessible to semi-automatic replacement. Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/strider.h')
-rw-r--r--include/configs/strider.h31
1 files changed, 6 insertions, 25 deletions
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 184396e037..1519dad321 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -167,19 +167,9 @@
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-/* Window base at flash base */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135
@@ -193,18 +183,9 @@
#define CONFIG_SYS_FPGA0_BASE 0xE0600000
#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
-/* Window base at FPGA base */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_TRLX_CLEAR \
- | OR_GPCM_EHTR_CLEAR)
+/* FPGA */
+#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k) 0x0010