diff options
| author | Allen Martin <amartin@nvidia.com> | 2012-08-31 08:30:12 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:22 +0200 |
| commit | 12b7b70cb01e284a7ca430d90f3e93bcc2daefec (patch) | |
| tree | 339e969b69c35cce8e84d5a8bda5be39e7e356bf /include/configs/tegra20-common.h | |
| parent | a49716aa7cda96f5e8cd15e57587da7a99f9e330 (diff) | |
tegra20: enable SPL for tegra20 boards
Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards. Also remove redundant code from u-boot that is not
contained in SPL.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/configs/tegra20-common.h')
| -rw-r--r-- | include/configs/tegra20-common.h | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 769728b35d..1c0d2350f4 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -43,8 +43,6 @@ #define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */ - #include <asm/arch/tegra20.h> /* get chip and board defs */ /* @@ -53,8 +51,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ @@ -182,7 +178,7 @@ #define PHYS_SDRAM_1 TEGRA20_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_TEXT_BASE 0x00108000 +#define CONFIG_SYS_TEXT_BASE 0x0010c000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE @@ -195,4 +191,20 @@ #define CONFIG_CMD_GPIO #define CONFIG_CMD_ENTERRCM #define CONFIG_CMD_BOOTZ + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x00108000 +#define CONFIG_SPL_MAX_SIZE 0x00004000 +#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 +#define CONFIG_SPL_STACK 0x000ffffc + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" + #endif /* __TEGRA20_COMMON_H */ |