diff options
author | Tom Rini <trini@konsulko.com> | 2019-03-19 07:14:37 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2019-04-12 08:05:55 -0400 |
commit | 9c4b0131d1d06dc87cecd08f065ec9b5c0f08b0f (patch) | |
tree | 2bc0d213b2173dccdc3356b7874672861da281cd /include/configs/ti_armv7_keystone2.h | |
parent | 55f8b70fee856f7fc2ccf452e3533814e98a1ac6 (diff) |
ti: keystone2: Move CONFIG_ISW_ENTRY_ADDR to a common place
The ISW_ENTRY_ADDR Kconfig option under mach-omap2 isn't a SoC specific
notion but rather "where is our previous stage loaded in memory?"
option. Make use of this on ARCH_KEYSTONE rather than SPL_TEXT_BASE for
our HS builds that are not using SPL anyhow.
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com?
Diffstat (limited to 'include/configs/ti_armv7_keystone2.h')
-rw-r--r-- | include/configs/ti_armv7_keystone2.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 52638cef4b..eeca085f9f 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -22,7 +22,7 @@ /* Memory Configuration */ #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_ISW_ENTRY_ADDR - \ GENERATED_GBL_DATA_SIZE) #ifdef CONFIG_SYS_MALLOC_F_LEN @@ -32,9 +32,10 @@ #endif /* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR #define CONFIG_SPL_PAD_TO 65536 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_ISW_ENTRY_ADDR + \ CONFIG_SPL_MAX_SIZE) #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ |