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authorSimon Glass <sjg@chromium.org>2016-03-16 07:44:43 -0600
committerBin Meng <bmeng.cn@gmail.com>2016-03-17 10:27:27 +0800
commit374e78efb0c6739c8c700325acca769d7a9e47de (patch)
tree4e626abc6d6bd43beec4b8bdad9025b4ef0e08e7 /include/configs/x86-chromebook.h
parente5aa8a9b1593f524af07318d4e84352b06a53402 (diff)
x86: Add support for the samus chromebook
This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'include/configs/x86-chromebook.h')
-rw-r--r--include/configs/x86-chromebook.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index c94096a349..312987edc8 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -21,7 +21,8 @@
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS