diff options
| author | Wolfgang Denk <wd@pollux.(none)> | 2005-09-23 11:05:55 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.(none)> | 2005-09-23 11:05:55 +0200 |
| commit | 0c8721a466b5e0eca7e7fbe1007777fa82100541 (patch) | |
| tree | 1f53decded27502be8593137739291a3de406d94 /include/configs | |
| parent | a6e6cf00367c0779eadb49915e40c55f0a787957 (diff) | |
Cleanup (PPC4xx is AMCC now)
Diffstat (limited to 'include/configs')
49 files changed, 52 insertions, 52 deletions
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h index 8d21b3f183..821efe5d48 100644 --- a/include/configs/ADCIOP.h +++ b/include/configs/ADCIOP.h @@ -184,7 +184,7 @@ * Cache Configuration */ #define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */ +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 2b389276fa..b53e85edae 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -263,7 +263,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/AR405.h b/include/configs/AR405.h index dfa62200e9..1cd0280e21 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -204,7 +204,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 8e3f34f98c..9841893899 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -264,7 +264,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 21bc4410c1..e0262a8f67 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -171,7 +171,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 776fce5a98..ffe89cb78f 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -409,7 +409,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 44a4d25b0c..4a6a3f8515 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -212,7 +212,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index b159182eb5..d49020db76 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -256,7 +256,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d1498eed3c..13dbe80daf 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -306,7 +306,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 29bd3da988..aaaafa94fd 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -278,7 +278,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 6673073c00..5cd9aba9e5 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -309,7 +309,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h index efb27cc61f..a5bc773e17 100644 --- a/include/configs/CPCI440.h +++ b/include/configs/CPCI440.h @@ -265,7 +265,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index ae54683b98..93d49f3862 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -187,7 +187,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h index 5ff9b9ecfc..997e1baa9a 100644 --- a/include/configs/DASA_SIM.h +++ b/include/configs/DASA_SIM.h @@ -183,7 +183,7 @@ * Cache Configuration */ #define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */ +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 6bebaaa76e..2ae794dc26 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -232,7 +232,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/DU405.h b/include/configs/DU405.h index a2512981fd..5489a53936 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -223,7 +223,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 1643dee4c9..c203aea924 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -323,7 +323,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index af96c7c70c..d9a7fb0fb8 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -321,7 +321,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 9ce6b3f891..e41e3712a3 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -359,7 +359,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 0fa5299187..eb627e881d 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -266,7 +266,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 2257ab24e5..060272cd18 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -269,7 +269,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 00a6e5d55d..7bbceb01bd 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -278,7 +278,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index cf6f00ef92..b96557148a 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -346,7 +346,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 6c2f17d587..db2147b481 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -257,7 +257,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 0x4000 /* For IBM 405GPr CPUs */ +#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ML2.h b/include/configs/ML2.h index 6e54d71e55..d8805ea5a7 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -193,7 +193,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 4a629e0997..aa9d1ba735 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -213,7 +213,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 4cc67bce2b..2e7c505f99 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -211,7 +211,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 469d88f292..9d5c4f4d04 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -241,7 +241,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 9ac57151cb..9668fb0ce2 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -224,7 +224,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 7ee95df11f..54ecfa4c5e 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -330,7 +330,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 4548ca69ff..8bcab0b0f3 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -245,7 +245,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 2d89f3ffaf..7ca827fa4b 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -422,7 +422,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index d8370ed66d..b3ce3da822 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -314,7 +314,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 4aade443fb..64b6c537ee 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -237,7 +237,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index ae3f1f43ae..8dc623ea06 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -275,7 +275,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 2a78082fe2..2bd98b3af3 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -276,7 +276,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 5c9950f6f8..d92f81f78e 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -265,7 +265,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 2e0b1a45f5..9b32514867 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -24,7 +24,7 @@ * config for XPedite1000 from XES Inc. * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com> * (C) Copyright 2003 Sandburst Corporation - * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony) + * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) ***********************************************************************/ #ifndef __CONFIG_H @@ -253,7 +253,7 @@ extern void out32(unsigned int, unsigned long); /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 440GX CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 910de67efd..29d333490c 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -378,7 +378,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index bc5aaf8934..5feb63a789 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -308,7 +308,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index ac1cead8d4..b4453b10ff 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -291,7 +291,7 @@ * Cache configuration * */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 4e5dcfcf07..a00cafbe2e 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -291,7 +291,7 @@ * Cache configuration * */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 1d4ea4e9b7..5f608be4c5 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -21,7 +21,7 @@ */ /************************************************************************ - * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony) + * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) ***********************************************************************/ #ifndef __CONFIG_H @@ -272,7 +272,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h index abad059ccf..6762cd61ea 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -147,7 +147,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ /*----------------------------------------------------------------------- diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 05a575bf63..5a27c02706 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -30,7 +30,7 @@ /************************************************************************ - * OCOTEA.h - configuration for IBM 440GX Ref (Ocotea) + * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea) ***********************************************************************/ #ifndef __CONFIG_H @@ -297,7 +297,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index aeb5126828..725b4937b3 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -226,7 +226,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 3a8e61c087..d33956d385 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -267,7 +267,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index 081cff88be..f2cd053e37 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -291,7 +291,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 4ac930b42a..5c9b0e9c8d 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -292,7 +292,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |