Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

6 files changed, 66 insertions, 10 deletions

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 2874ccc6fa..3dc4da391b 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -510,6 +510,30 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS		0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE	0x08000000	/* 128M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 0a0bb5f109..a13876b550 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -303,6 +303,30 @@
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS		0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE	0x08000000	/* 128M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 6fe032c9ff..17a1cde039 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -13,6 +13,7 @@
 #define CONFIG_FSL_LSCH3
 #define CONFIG_LS2085A
 #define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
 
 /* Link Definitions */
 #define CONFIG_SYS_TEXT_BASE		0x30001000
@@ -26,9 +27,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F	1
 
-#define CONFIG_IDENT_STRING		" LS2085A-EMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-EMU"
-
 /* Flat Device Tree Definitions */
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
@@ -209,12 +207,10 @@
 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
 #define CONFIG_SYS_LS_MC_FW_IN_NOR
 #define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL
-/* TODO Actual FW length needs to be determined at runtime from FW header */
-#define CONFIG_SYS_LS_MC_FW_LENGTH	(4U * 1024 * 1024)
 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
 #define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPL_LENGTH	4096
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	(256 * 1024)
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0xe00000
 
 /* Carve the MC private DRAM block from the end of DRAM */
@@ -248,7 +244,8 @@
 /* Physical Memory Map */
 /* fixme: these need to be checked against the board */
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
-#define CONFIG_SYS_CLK_FREQ	133333333
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133333333
 
 
 #define CONFIG_NR_DRAM_BANKS		3
@@ -268,12 +265,14 @@
 	"fdt_high=0xffffffffffffffff\0"		\
 	"initrd_high=0xffffffffffffffff\0"	\
 	"kernel_start=0x581200000\0"		\
-	"kernel_load=0x806f0000\0"		\
+	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x1000000\0"		\
 	"console=ttyAMA0,38400n8\0"
 
-#define CONFIG_BOOTARGS			"console=ttyS1,115200 root=/dev/ram0 " \
-					"earlyprintk=uart8250-8bit,0x21c0600"
+#define CONFIG_BOOTARGS		"console=ttyS1,115200 root=/dev/ram0 " \
+				"earlycon=uart8250,mmio,0x21c0600,115200 " \
+				"default_hugepagesz=2m hugepagesz=2m " \
+				"hugepages=16"
 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
 					"$kernel_size && bootm $kernel_load"
 #define CONFIG_BOOTDELAY		1
diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h
index 487cd99c5d..a02d69450b 100644
--- a/include/configs/ls2085a_emu.h
+++ b/include/configs/ls2085a_emu.h
@@ -9,6 +9,9 @@
 
 #include "ls2085a_common.h"
 
+#define CONFIG_IDENT_STRING		" LS2085A-EMU"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-EMU"
+
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_EMU		/* Support emulator */
 #define SPD_EEPROM_ADDRESS1	0x51
@@ -17,4 +20,5 @@
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
 
+#define CONFIG_FSL_DDR_SYNC_REFRESH
 #endif /* __LS2_EMU_H */
diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h
index 0f40b787b4..af34f3f95d 100644
--- a/include/configs/ls2085a_simu.h
+++ b/include/configs/ls2085a_simu.h
@@ -9,6 +9,9 @@
 
 #include "ls2085a_common.h"
 
+#define CONFIG_IDENT_STRING		" LS2085A-SIMU"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-SIMU"
+
 /* SMSC 91C111 ethernet configuration */
 #define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE	(0x2210000)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index e0528ce4b9..29b72b2e9d 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -28,6 +28,8 @@
 #define CONFIG_SYS_PL310_BASE	L2_PL310_BASE
 #endif
 
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+
 #define CONFIG_MP
 #define CONFIG_MXC_GPT_HCLK