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authorYork Sun <york.sun@nxp.com>2016-10-04 18:03:08 -0700
committerYork Sun <york.sun@nxp.com>2016-10-06 09:59:11 -0700
commit24aaa09452162c18921d8771ac29d13be1e5dc0d (patch)
tree5aebb9dce7ef06d15d28fdb9fa382a53637ba0d3 /include/configs
parentf534b8f5fdabfbe47c9c741864ed52e945afbd27 (diff)
armv8: fsl-layerscape: Move DDR config options to Kconfig
Move DDR3, DDR4 and realted options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/ls1043a_common.h4
-rw-r--r--include/configs/ls1043aqds.h3
-rw-r--r--include/configs/ls2080a_common.h1
3 files changed, 0 insertions, 8 deletions
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 3a85b6a8ef..0fd69bff4b 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -24,10 +24,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F 1
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
-#endif
-
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index b18fcc0c2f..b80e3165a9 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -42,9 +42,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
-#endif
#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 187aee1469..3dd4da840d 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -46,7 +46,6 @@
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif