diff options
| author | York Sun <yorksun@freescale.com> | 2010-10-18 13:46:49 -0700 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-10-20 02:38:39 -0500 |
| commit | 28a966715be78fc35147086e68fc80aeb21235b1 (patch) | |
| tree | 28351553e38981202b6afb5f42e33f9e036dfe2d /include/configs | |
| parent | 84bc00300f2e0fa0a2d5907589fdff613f72e704 (diff) | |
Adding fixed sdram setting for cornet_ds board
800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram
setting. SPD based parameters and fixed parameters can be toggled by hwconfig.
To use fixed parameters,
hwconfig=fsl_ddr:sdram=fixed
To use SPD parameters,
hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/corenet_ds.h | 60 |
1 files changed, 1 insertions, 59 deletions
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c85bffce09..85147d0021 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -130,68 +130,10 @@ #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 -#ifdef CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 -#else -#define CONFIG_SYS_SDRAM_SIZE 4096 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x01031000 -#define CONFIG_SYS_DDR_TIMING_0 0x55440804 -#define CONFIG_SYS_DDR_TIMING_1 0x74713a66 -#define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b -#define CONFIG_SYS_DDR_MODE_1 0x00421850 -#define CONFIG_SYS_DDR_MODE_2 0x00100000 -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x10400100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03401500 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608 -#define CONFIG_SYS_DDR_CONTROL 0xc7048000 -#define CONFIG_SYS_DDR_CONTROL2 0x24400011 -#define CONFIG_SYS_DDR_CDR1 0x00000000 -#define CONFIG_SYS_DDR_CDR2 0x00000000 -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 -#define CONFIG_SYS_DDR_DEBUG_18 0x40100400 - -#define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff -#define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG -#define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG -#define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3 -#define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0 -#define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1 -#define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2 -#define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1 -#define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2 -#define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL -#define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL -#define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT -#define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL -#define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4 -#define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5 -#define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL -#define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL -#define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL -#define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2 -#define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1 -#define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2 -#define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN -#define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS -#define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE -#define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18 - -#endif +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * Local Bus Definitions |