diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2012-02-07 14:08:50 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-27 21:19:25 +0100 |
| commit | 2bf3359ea5555972bcd6684f1c3142e2b7200281 (patch) | |
| tree | 0fc507d61c9deba9fa71849930b30c30c4243100 /include/configs | |
| parent | 9fafe7dab9bc8a9e33e1ba5e28a3ec870d689b82 (diff) | |
i.mx6q: mx6qsabrelite: Update the network configuration
Define CONFIG_PHY_MICREL, and
minimize the tx clock delay.
There is an issue with 1000 baseTx mode on early revs
of the SabreLite boards. The center tap pin 9 of the mag RJ45
USB combo was connected to the 3.3 filtered supply. Letting
this pin float solved the problem. Symptoms of the problem
were packets with many extra zeroes tacked on the end, and random
bit flips causing a high rate of CRC errors. 10/100 baseTx worked
fine on all revs. To disable 1000 baseTx for these boards, simply
define the environment variable disable_giga. ie.
setenv disable_giga 1
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/mx6qsabrelite.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 8a95af91cc..982f03f710 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -77,6 +77,8 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE |