diff options
| author | Priyanka Jain <priyanka.jain@nxp.com> | 2017-04-27 15:08:07 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-05-23 09:47:08 -0700 |
| commit | 3049a583f343a71ead9d7cb33f0ab6cecfbbaa12 (patch) | |
| tree | 8cd1822e41925299bd43a63d213e0be10bf2ceff /include/configs | |
| parent | e809e747996b00acd0ffc833999e97a3a21ddfac (diff) | |
armv8: ls2080ardb: Add LS2081ARDB board support
LS2081ARDB board is similar to LS2080ARDB board with few differences
It hosts LS2081A SoC
Default boot source is QSPI-boot
It does not have IFC interface
RTC and QSPI flash device are different
It provides QIXIS access via I2C
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/ls2080ardb.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index ef95358ebf..3774b177fc 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -14,6 +14,9 @@ #define CONFIG_CONS_INDEX 2 #ifdef CONFIG_FSL_QSPI +#ifdef CONFIG_TARGET_LS2081ARDB +#define CONFIG_QIXIS_I2C_ACCESS +#endif #define CONFIG_SYS_I2C_EARLY_INIT #define CONFIG_DISPLAY_BOARDINFO_LATE #endif @@ -259,9 +262,28 @@ unsigned long get_board_sys_clk(void); #endif #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#ifdef CONFIG_TARGET_LS2081ARDB +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_QMAP_MASK 0x07 +#define QIXIS_QMAP_SHIFT 5 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_QSPI 0x62 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_RST_CTL_RESET_EN 0x30 +#endif + /* * I2C */ +#ifdef CONFIG_TARGET_LS2081ARDB +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#endif #define I2C_MUX_PCA_ADDR 0x75 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ @@ -275,7 +297,11 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SPI_FLASH_STMICRO #endif #ifdef CONFIG_FSL_QSPI +#ifdef CONFIG_TARGET_LS2081ARDB +#define CONFIG_SPI_FLASH_STMICRO +#else #define CONFIG_SPI_FLASH_SPANSION +#endif #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ #define FSL_QSPI_FLASH_NUM 2 #endif @@ -285,8 +311,13 @@ unsigned long get_board_sys_clk(void); * RTC configuration */ #define RTC +#ifdef CONFIG_TARGET_LS2081ARDB +#define CONFIG_RTC_PCF8563 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#else #define CONFIG_RTC_DS3231 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#endif /* EEPROM */ #define CONFIG_ID_EEPROM |