diff options
| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-12-14 16:16:49 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-12-19 15:23:01 +0100 |
| commit | 6787c1ece07f771629ea5b463a362f9b4c40d2c0 (patch) | |
| tree | 1340a0d0907ae67cb47ef62732a798790c8145a7 /include/configs | |
| parent | 6bd8231a6dd58c2003e67a84e55705014d963989 (diff) | |
MSCC: add board support for the Ocelots based evaluation boards
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/vcoreiii.h | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h new file mode 100644 index 0000000000..df89cdaebf --- /dev/null +++ b/include/configs/vcoreiii.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef __VCOREIII_H +#define __VCOREIII_H + +#include <linux/sizes.h> + +/* Onboard devices */ + +#define CONFIG_SYS_MALLOC_LEN 0x100000 +#define CONFIG_SYS_LOAD_ADDR 0x00100000 +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */ +#ifdef CONFIG_SOC_LUTON +#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333 +#else +#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) +#endif +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_SIZE (256 * 1024) +#define CONFIG_ENV_SECT_SIZE (256 * 1024) + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_SPI_MAX_HZ 0 /* This force to read from DT */ +#define CONFIG_ENV_SPI_MODE 0 /* This force to read from DT */ +#endif + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) +#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT) +#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M) +#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16) +#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M) +#else +#error Unknown DDR size - please add! +#endif + +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_BOARD_EARLY_INIT_R +#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) +#define VCOREIII_DEFAULT_MTD_ENV \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ + "mtdids="CONFIG_MTDIDS_DEFAULT"\0" +#else +#define VCOREIII_DEFAULT_MTD_ENV /* Go away */ +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + VCOREIII_DEFAULT_MTD_ENV \ + "loadaddr=0x81000000\0" \ + "spi_image_off=0x00100000\0" \ + "console=ttyS0,115200\0" \ + "setup=setenv bootargs console=${console} ${mtdparts}" \ + "${bootargs_extra}\0" \ + "spiboot=run setup; sf probe; sf read ${loadaddr}" \ + "${spi_image_off} 0x600000; bootm ${loadaddr}\0" \ + "ubootfile=u-boot.bin\0" \ + "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \ + "sf erase UBoot 0x100000;" \ + "sf write ${loadaddr} UBoot ${filesize}\0" \ + "bootcmd=run spiboot\0" \ + "" +#endif /* __VCOREIII_H */ |