diff options
| author | Mingkai Hu <Mingkai.Hu@freescale.com> | 2015-10-26 19:47:50 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-10-29 10:34:00 -0700 |
| commit | 9f3183d2d69f6d392fb943d249934f8648531e7e (patch) | |
| tree | a122bb60c3b3df518d476a1fa971e3ba17365c7f /include/configs | |
| parent | 23e1acaf4b2863917247a925c81f6ce5a4eadcc2 (diff) | |
armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/ls2085a_common.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index a918b18379..0011e720ea 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -9,8 +9,10 @@ #define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LSCH3 #define CONFIG_LS2085A +#define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 @@ -18,12 +20,15 @@ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 -#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h> -#include <asm/arch-fsl-lsch3/config.h> +#include <asm/arch/ls2085a_stream_id.h> +#include <asm/arch/config.h> #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) #define CONFIG_SYS_HAS_SERDES #endif +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT @@ -62,6 +67,7 @@ #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ +#define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |