diff options
| author | York Sun <yorksun@freescale.com> | 2013-06-25 11:37:48 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:39 -0700 |
| commit | c63e137014cf148bc1d234128941dccee3d519ae (patch) | |
| tree | afb69c22c33459d14a174973083e2a70e5f49ea7 /include/configs | |
| parent | b61e06156660579ea6e248abd2506ebdd85e7a14 (diff) | |
powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/T4240QDS.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 2cf4a69f2a..d92de3596c 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -161,6 +161,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RST_FORCE_MEM 0x1 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |