diff options
| author | Stefan Roese <sr@denx.de> | 2015-01-19 11:33:47 +0100 |
|---|---|---|
| committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-02-06 17:24:43 +0100 |
| commit | e7778ec153e279e451bf7c55c05c76e76b095875 (patch) | |
| tree | 21d1e37f94d7c6a98a87d38333f86959f2ed20da /include/configs | |
| parent | 2f20aa82f470c0f6b5592914b9c4c3fd07bcb722 (diff) | |
arm: maxbcm: Enable SPL to include DDR training code into U-Boot
This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/maxbcm.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 72217bdb57..4e962a3604 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -65,4 +65,51 @@ */ #include "mv-common.h" +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40004030 +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds" + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ + #endif /* _CONFIG_DB_MV7846MP_GP_H */ |