diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2016-06-22 02:29:47 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2016-07-11 14:06:44 -0600 |
| commit | 6f0e7a36efbb30fb7a100f5a6f421b0310815815 (patch) | |
| tree | a92a0a641bdfe52340d334dfae8a6bf6e27edb6f /include/dm/uclass-id.h | |
| parent | 920c6965d11137fff45feccee7e1108875b196d0 (diff) | |
dm: Sort the uclass id in alphabetical order
Some uclass ids are out of order. Per the comments, sort them
in alphabetical order.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/dm/uclass-id.h')
| -rw-r--r-- | include/dm/uclass-id.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index b768660e85..c5cdfc79d1 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -33,7 +33,6 @@ enum uclass_id { UCLASS_CROS_EC, /* Chrome OS EC */ UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */ UCLASS_DMA, /* Direct Memory Access */ - UCLASS_RAM, /* RAM controller */ UCLASS_ETH, /* Ethernet device */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_I2C, /* I2C bus */ @@ -56,11 +55,12 @@ enum uclass_id { UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ - UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ UCLASS_PINCONFIG, /* Pin configuration node device */ + UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ UCLASS_PMIC, /* PMIC I/O device */ UCLASS_PWM, /* Pulse-width modulator */ UCLASS_PWRSEQ, /* Power sequence device */ + UCLASS_RAM, /* RAM controller */ UCLASS_REGULATOR, /* Regulator device */ UCLASS_REMOTEPROC, /* Remote Processor device */ UCLASS_RESET, /* Reset controller device */ |