diff options
| author | Simon Glass <sjg@chromium.org> | 2019-12-06 21:41:55 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:11 +0800 |
| commit | 5bee27aa41eeafb71f1d467f81f7fae6ee8cfa6d (patch) | |
| tree | 5db81fff6d52cc7ee4f9f707eaaa82d90e930dfb /include/dm | |
| parent | 3b65ee34b908ce0c495c25987f5feb37ac163eab (diff) | |
pci: Add support for p2sb uclass
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.
This adds a uclass and enables it for sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'include/dm')
| -rw-r--r-- | include/dm/uclass-id.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 8431ad9c44..c1bab17ad1 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -70,6 +70,7 @@ enum uclass_id { UCLASS_NOP, /* No-op devices */ UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */ UCLASS_NVME, /* NVM Express device */ + UCLASS_P2SB, /* (x86) Primary-to-Sideband Bus */ UCLASS_PANEL, /* Display panel, such as an LCD */ UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */ UCLASS_PCH, /* x86 platform controller hub */ |