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authorHeiko Stübner <heiko@sntech.de>2017-02-18 19:46:33 +0100
committerSimon Glass <sjg@chromium.org>2017-03-16 16:03:45 -0600
commit7b2500babd6b9fce7ef9ae43132d42279442edc9 (patch)
tree501b42f9c0caa592174b91b468c5b1c1367afbd2 /include/dt-bindings/clock/rk3188-cru.h
parent37c07c5b1ff89a75581a236d1536b0584d2f74c0 (diff)
rockchip: rk3188: Add rk3066/rk3188 clock bindings
Bring in required device clock binding files from Linux. The clock trees for rk3066 and rk3188 are largely similar, which makes them share the common parts in a shared header. While we focus on rk3188 for now, bring in both headers already for completeness sake. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'include/dt-bindings/clock/rk3188-cru.h')
-rw-r--r--include/dt-bindings/clock/rk3188-cru.h48
1 files changed, 48 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h
new file mode 100644
index 0000000000..b6960b07bc
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+
+#include <dt-bindings/clock/rk3188-cru-common.h>
+
+/* soft-reset indices */
+#define SRST_PTM_CORE2 0
+#define SRST_PTM_CORE3 1
+#define SRST_CORE2 5
+#define SRST_CORE3 6
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+
+#define SRST_TIMER2 16
+#define SRST_TIMER4 23
+#define SRST_I2S0 24
+#define SRST_TIMER5 25
+#define SRST_TIMER3 29
+#define SRST_TIMER6 31
+
+#define SRST_PTM3 36
+#define SRST_PTM3_ATB 37
+
+#define SRST_GPS 67
+#define SRST_HSICPHY 75
+#define SRST_TIMER 78
+
+#define SRST_PTM2 92
+#define SRST_CORE2_WDT 94
+#define SRST_CORE3_WDT 95
+
+#define SRST_PTM2_ATB 111
+
+#define SRST_HSIC 117
+#define SRST_CTI2 118
+#define SRST_CTI2_APB 119
+#define SRST_GPU_BRIDGE 121
+#define SRST_CTI3 123
+#define SRST_CTI3_APB 124
+
+#endif