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authorMichal Simek <michal.simek@xilinx.com>2018-07-18 13:27:24 +0200
committerMichal Simek <michal.simek@xilinx.com>2018-10-16 14:58:45 +0200
commit0e4c1dd29026ee76b2ae8fb27a99366ac7d0b289 (patch)
tree5c79372be4b2ccad94cee1721ca8de0325a2c9fa /include/fis.h
parent3313ae668e0071f91cdf305fedb39b960beab62d (diff)
arm: zynq: Enable FIT fpga loading in SPL for zc706
Enable loading FPGA from FIT image in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'include/fis.h')
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