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authorVladimir Oltean <vladimir.oltean@nxp.com>2020-05-04 11:24:26 +0300
committerPriyanka Jain <priyanka.jain@nxp.com>2020-07-27 14:16:26 +0530
commite7005b3e80d396f45a3ba88448818eee5d592f27 (patch)
tree549c06c99dd8522ac8b9099b106b2fc46b96eff5 /include/fsl_dspi.h
parentada61f1ee2a4eaa1b29d699b5ba940483171df8a (diff)
fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delays
Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'include/fsl_dspi.h')
-rw-r--r--include/fsl_dspi.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/fsl_dspi.h b/include/fsl_dspi.h
index 114f63bce3..4fec83549e 100644
--- a/include/fsl_dspi.h
+++ b/include/fsl_dspi.h
@@ -94,6 +94,7 @@ struct dspi {
#define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8)
#define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4)
#define DSPI_CTAR_BR(x) ((x) & 0x0F)
+#define DSPI_CTAR_SCALE_BITS 0xf
/* Status */
#define DSPI_SR_TCF 0x80000000