mmc: fsl_esdhc: support SDR104 and HS200

Introduce SDR104 and HS200 support
The implementation takes linux kernel sdhci.c and sdhci-esdhc-imx.c
as reference.
 - Implement esdhc_change_pinstate to dynamically change pad settings
 - Implement esdhc_set_timing
 - Implement esdhc_set_voltage to switch voltage
 - Implement fsl_esdhc_execute_tuning to execute time process
 - Enlarge the cfg->f_max to 200MHz.
 - Parse fsl,tuning-step, fsl,tuning-start-tap and
   fsl,strobe-dll-delay-target from device tree.
 - Parse no-1-8-v property
 - Introduce esdhc_soc_data to indicate the flags and caps

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

1 files changed, 47 insertions, 0 deletions

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index de1f5e7d9f..b341e018f2 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -10,6 +10,7 @@
 #ifndef  __FSL_ESDHC_H__
 #define	__FSL_ESDHC_H__
 
+#include <linux/bitops.h>
 #include <linux/errno.h>
 #include <asm/byteorder.h>
 
@@ -173,6 +174,52 @@
 
 #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
 
+/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
+#define	MIX_CTRL_DDREN		BIT(3)
+#define MIX_CTRL_DTDSEL_READ	BIT(4)
+#define	MIX_CTRL_AC23EN		BIT(7)
+#define	MIX_CTRL_EXE_TUNE	BIT(22)
+#define	MIX_CTRL_SMPCLK_SEL	BIT(23)
+#define	MIX_CTRL_AUTO_TUNE_EN	BIT(24)
+#define	MIX_CTRL_FBCLK_SEL	BIT(25)
+#define	MIX_CTRL_HS400_EN	BIT(26)
+#define	MIX_CTRL_HS400_ES	BIT(27)
+/* Bits 3 and 6 are not SDHCI standard definitions */
+#define	MIX_CTRL_SDHCI_MASK	0xb7
+/* Tuning bits */
+#define	MIX_CTRL_TUNING_MASK	0x03c00000
+
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL		0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE	BIT(0)
+#define ESDHC_STROBE_DLL_CTRL_RESET	BIT(1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT	0x7
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3
+
+#define ESDHC_STROBE_DLL_STATUS		0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK	BIT(1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK	0x1
+#define ESDHC_STROBE_DLL_CLK_FREQ	100000000
+
+#define ESDHC_STD_TUNING_EN             BIT(24)
+/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
+#define ESDHC_TUNING_START_TAP_DEFAULT	0x1
+#define ESDHC_TUNING_START_TAP_MASK	0xff
+#define ESDHC_TUNING_STEP_MASK		0x00070000
+#define ESDHC_TUNING_STEP_SHIFT		16
+
+#define	ESDHC_FLAG_MULTIBLK_NO_INT	BIT(1)
+#define	ESDHC_FLAG_ENGCM07207		BIT(2)
+#define	ESDHC_FLAG_USDHC		BIT(3)
+#define	ESDHC_FLAG_MAN_TUNING		BIT(4)
+#define	ESDHC_FLAG_STD_TUNING		BIT(5)
+#define	ESDHC_FLAG_HAVE_CAP1		BIT(6)
+#define	ESDHC_FLAG_ERR004536		BIT(7)
+#define	ESDHC_FLAG_HS200		BIT(8)
+#define	ESDHC_FLAG_HS400		BIT(9)
+#define	ESDHC_FLAG_ERR010450		BIT(10)
+#define	ESDHC_FLAG_HS400_ES		BIT(11)
+
 struct fsl_esdhc_cfg {
 	phys_addr_t esdhc_base;
 	u32	sdhc_clk;