diff options
| author | Andrew Gabbasov <andrew_gabbasov@mentor.com> | 2013-04-07 23:06:08 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-04-14 11:22:47 +0200 |
| commit | 9b74dc56fba2b9db39420f81c990284f36d5801f (patch) | |
| tree | de12f8c9a57135903b70ae9895fdc8a97397fee7 /include/fsl_esdhc.h | |
| parent | 54899fc8fe7b33cbe1a7179e39d24e75ababcdc6 (diff) | |
fsl_esdhc: Fix DMA transfer completion waiting loop
Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can be removed from the condition. Also, DMA Error
condition is added to the list of data errors, checked in the loop.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Diffstat (limited to 'include/fsl_esdhc.h')
| -rw-r--r-- | include/fsl_esdhc.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 0a1a0715e9..67d6057b5f 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -63,7 +63,9 @@ #define IRQSTAT_CC (0x00000001) #define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) -#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE) +#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \ + IRQSTAT_DMAE) +#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT) #define IRQSTATEN 0x0002e034 #define IRQSTATEN_DMAE (0x10000000) |