diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2020-06-22 19:38:03 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-06-24 14:05:30 +0800 |
| commit | 135c10a7834aa7e0f26f52e5173925e695cba48f (patch) | |
| tree | 45be55e8c718c296da97e0857bb5841e6b125c96 /include/fsl_esdhc_imx.h | |
| parent | d581076a33e7fd1f2b019a0a53eebe58d76623c1 (diff) | |
mmc: fsl_esdhc_imx: fix the mask for tuning start point
According the RM, the bit[6~0] of register ESDHC_TUNING_CTRL is
TUNING_START_TAP, bit[7] of this register is to disable the command
CRC check for standard tuning. So fix it here.
Fixes: fa33d207494c ("mmc: split fsl_esdhc driver for i.MX")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Diffstat (limited to 'include/fsl_esdhc_imx.h')
| -rw-r--r-- | include/fsl_esdhc_imx.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 33c6d52bfe..220a76b9ee 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -203,7 +203,7 @@ #define ESDHC_STD_TUNING_EN BIT(24) /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 -#define ESDHC_TUNING_START_TAP_MASK 0xff +#define ESDHC_TUNING_START_TAP_MASK 0x7f #define ESDHC_TUNING_STEP_MASK 0x00070000 #define ESDHC_TUNING_STEP_SHIFT 16 |