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authorStefan Agner <stefan@agner.ch>2014-04-23 18:17:51 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-05-25 15:46:12 +0200
commit56d83d1c046c693b65ab09c0e960d922ec639c2b (patch)
tree87c48bc6742a97768be857d92f18976665d3feef /include/galileo
parent1277bac0d21bfa6952bdb14fcbf4134aa3018056 (diff)
arm: vf610: add DDR_SEL_PAD_CONTR register
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual. Signed-off-by: Stefan Agner <stefan@agner.ch>
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