summaryrefslogtreecommitdiff
path: root/include/gdsys_fpga.h
diff options
context:
space:
mode:
authorLukas Auer <lukas.auer@aisec.fraunhofer.de>2018-11-22 11:26:12 +0100
committerAndes <uboot@andestech.com>2018-11-26 13:57:29 +0800
commit862e2e75e8f317ff8bd660550d7da3fede2ead09 (patch)
tree1c7affaf8b45a246101e92d149e5abc1c85267c1 /include/gdsys_fpga.h
parent17f2ffea36bf9d2ef7238cfd52b8872cbb50034a (diff)
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'include/gdsys_fpga.h')
0 files changed, 0 insertions, 0 deletions