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authorSimon Glass <sjg@chromium.org>2020-05-10 11:40:13 -0600
committerTom Rini <trini@konsulko.com>2020-05-18 21:19:23 -0400
commitcd93d625fd751d55c729c78b10f82109d56a5f1d (patch)
tree158fd30f3d06142f6a99cbae6ed8ccb0f3be567b /include/net
parentf09f1ecbe77863ecefe586ccd6000064b49105a3 (diff)
common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/net')
-rw-r--r--include/net/pfe_eth/pfe/cbus/class_csr.h1
-rw-r--r--include/net/pfe_eth/pfe/cbus/emac.h1
-rw-r--r--include/net/pfe_eth/pfe/cbus/hif.h1
-rw-r--r--include/net/pfe_eth/pfe/cbus/tmu_csr.h1
-rw-r--r--include/net/pfe_eth/pfe/pfe_hw.h1
-rw-r--r--include/net/pfe_eth/pfe_eth.h1
6 files changed, 6 insertions, 0 deletions
diff --git a/include/net/pfe_eth/pfe/cbus/class_csr.h b/include/net/pfe_eth/pfe/cbus/class_csr.h
index e2fece7aa1..80f1f96b44 100644
--- a/include/net/pfe_eth/pfe/cbus/class_csr.h
+++ b/include/net/pfe_eth/pfe/cbus/class_csr.h
@@ -12,6 +12,7 @@
* class_csr - block containing all the classifier control and status register.
* Mapped on CBUS and accessible from all PE's and ARM.
*/
+#include <linux/bitops.h>
#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
diff --git a/include/net/pfe_eth/pfe/cbus/emac.h b/include/net/pfe_eth/pfe/cbus/emac.h
index 53db8cc08f..5dc2113687 100644
--- a/include/net/pfe_eth/pfe/cbus/emac.h
+++ b/include/net/pfe_eth/pfe/cbus/emac.h
@@ -7,6 +7,7 @@
#ifndef _EMAC_H_
#define _EMAC_H_
+#include <linux/bitops.h>
#define EMAC_IEVENT_REG 0x004
#define EMAC_IMASK_REG 0x008
#define EMAC_R_DES_ACTIVE_REG 0x010
diff --git a/include/net/pfe_eth/pfe/cbus/hif.h b/include/net/pfe_eth/pfe/cbus/hif.h
index 36722c5e07..aa4951ec0e 100644
--- a/include/net/pfe_eth/pfe/cbus/hif.h
+++ b/include/net/pfe_eth/pfe/cbus/hif.h
@@ -12,6 +12,7 @@
* hif - PFE hif block control and status register.
* Mapped on CBUS and accessible from all PE's and ARM.
*/
+#include <linux/bitops.h>
#define HIF_VERSION (HIF_BASE_ADDR + 0x00)
#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
diff --git a/include/net/pfe_eth/pfe/cbus/tmu_csr.h b/include/net/pfe_eth/pfe/cbus/tmu_csr.h
index 1e1abe26ca..cfe8f8ce8f 100644
--- a/include/net/pfe_eth/pfe/cbus/tmu_csr.h
+++ b/include/net/pfe_eth/pfe/cbus/tmu_csr.h
@@ -7,6 +7,7 @@
#ifndef _TMU_CSR_H_
#define _TMU_CSR_H_
+#include <linux/bitops.h>
#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
diff --git a/include/net/pfe_eth/pfe/pfe_hw.h b/include/net/pfe_eth/pfe/pfe_hw.h
index 5da676bf8b..c69fc69130 100644
--- a/include/net/pfe_eth/pfe/pfe_hw.h
+++ b/include/net/pfe_eth/pfe/pfe_hw.h
@@ -8,6 +8,7 @@
#define _PFE_H_
#include <elf.h>
+#include <linux/bitops.h>
#include "cbus.h"
#define PFE_RESET_WA
diff --git a/include/net/pfe_eth/pfe_eth.h b/include/net/pfe_eth/pfe_eth.h
index 68b2e381b9..116a2b2c1d 100644
--- a/include/net/pfe_eth/pfe_eth.h
+++ b/include/net/pfe_eth/pfe_eth.h
@@ -7,6 +7,7 @@
#ifndef __PFE_ETH_H__
#define __PFE_ETH_H__
+#include <linux/bitops.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <miiphy.h>