diff options
author | Patrick Delaunay <patrick.delaunay@st.com> | 2019-02-04 11:26:17 +0100 |
---|---|---|
committer | Patrick Delaunay <patrick.delaunay@st.com> | 2019-04-12 16:09:13 +0200 |
commit | 42f01aacfd508ddaab5fbc21dd1d3c04dcf61990 (patch) | |
tree | 801b63d1531d916cc5bc56eb86d85bf1d55716a3 /include/power/stpmic1.h | |
parent | d46c22b3fdb58623f1bf372d028313a5d3e7b79b (diff) |
power: rename stpmu1 to official name stpmic1
Alignment with kernel driver name & binding
introduced by https://patchwork.kernel.org/cover/10761943/
to use the final marketing name = STPMIC1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Diffstat (limited to 'include/power/stpmic1.h')
-rw-r--r-- | include/power/stpmic1.h | 135 |
1 files changed, 71 insertions, 64 deletions
diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h index 5906fbf832..5ed67d29cf 100644 --- a/include/power/stpmic1.h +++ b/include/power/stpmic1.h @@ -3,83 +3,90 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#ifndef __PMIC_STPMU1_H_ -#define __PMIC_STPMU1_H_ - -#define STPMU1_MASK_RESET_BUCK 0x18 -#define STPMU1_BUCKX_CTRL_REG(buck) (0x20 + (buck)) -#define STPMU1_VREF_CTRL_REG 0x24 -#define STPMU1_LDOX_CTRL_REG(ldo) (0x25 + (ldo)) -#define STPMU1_USB_CTRL_REG 0x40 -#define STPMU1_NVM_USER_STATUS_REG 0xb8 -#define STPMU1_NVM_USER_CONTROL_REG 0xb9 - -#define STPMU1_MASK_RESET_BUCK3 BIT(2) - -#define STPMU1_BUCK_EN BIT(0) -#define STPMU1_BUCK_MODE BIT(1) -#define STPMU1_BUCK_OUTPUT_MASK GENMASK(7, 2) -#define STPMU1_BUCK_OUTPUT_SHIFT 2 -#define STPMU1_BUCK2_1200000V (24 << STPMU1_BUCK_OUTPUT_SHIFT) -#define STPMU1_BUCK2_1350000V (30 << STPMU1_BUCK_OUTPUT_SHIFT) -#define STPMU1_BUCK3_1800000V (39 << STPMU1_BUCK_OUTPUT_SHIFT) - -#define STPMU1_VREF_EN BIT(0) - -#define STPMU1_LDO_EN BIT(0) -#define STPMU1_LDO12356_OUTPUT_MASK GENMASK(6, 2) -#define STPMU1_LDO12356_OUTPUT_SHIFT 2 -#define STPMU1_LDO3_MODE BIT(7) -#define STPMU1_LDO3_DDR_SEL 31 -#define STPMU1_LDO3_1800000 (9 << STPMU1_LDO12356_OUTPUT_SHIFT) -#define STPMU1_LDO4_UV 3300000 - -#define STPMU1_USB_BOOST_EN BIT(0) -#define STPMU1_USB_PWR_SW_EN GENMASK(2, 1) - -#define STPMU1_NVM_USER_CONTROL_PROGRAM BIT(0) -#define STPMU1_NVM_USER_CONTROL_READ BIT(1) - -#define STPMU1_NVM_USER_STATUS_BUSY BIT(0) -#define STPMU1_NVM_USER_STATUS_ERROR BIT(1) - -#define STPMU1_DEFAULT_START_UP_DELAY_MS 1 -#define STPMU1_DEFAULT_STOP_DELAY_MS 5 -#define STPMU1_USB_BOOST_START_UP_DELAY_MS 10 +#ifndef __PMIC_STPMIC1_H_ +#define __PMIC_STPMIC1_H_ + +#define STPMIC1_MAIN_CONTROL_REG 0x10 +#define STPMIC1_MASK_RESET_BUCK 0x18 +#define STPMIC1_MASK_RESET_LDOS 0x1a +#define STPMIC1_BUCKX_CTRL_REG(buck) (0x20 + (buck)) +#define STPMIC1_VREF_CTRL_REG 0x24 +#define STPMIC1_LDOX_CTRL_REG(ldo) (0x25 + (ldo)) +#define STPMIC1_USB_CTRL_REG 0x40 +#define STPMIC1_NVM_USER_STATUS_REG 0xb8 +#define STPMIC1_NVM_USER_CONTROL_REG 0xb9 + +/* Main PMIC Control Register (MAIN_CONTROL_REG) */ +#define STPMIC1_CTRL_SWITCH_OFF BIT(0) +#define STPMIC1_CTRL_RESTART BIT(1) + +#define STPMIC1_MASK_RESET_BUCK3 BIT(2) +#define STPMIC1_MASK_RESET_BUCK_DBG GENMASK(3, 0) +#define STPMIC1_MASK_RESET_LDOS_DBG 0x6F + +#define STPMIC1_BUCK_EN BIT(0) +#define STPMIC1_BUCK_MODE BIT(1) +#define STPMIC1_BUCK_OUTPUT_MASK GENMASK(7, 2) +#define STPMIC1_BUCK_OUTPUT_SHIFT 2 +#define STPMIC1_BUCK2_1200000V (24 << STPMIC1_BUCK_OUTPUT_SHIFT) +#define STPMIC1_BUCK2_1350000V (30 << STPMIC1_BUCK_OUTPUT_SHIFT) +#define STPMIC1_BUCK3_1800000V (39 << STPMIC1_BUCK_OUTPUT_SHIFT) + +#define STPMIC1_VREF_EN BIT(0) + +#define STPMIC1_LDO_EN BIT(0) +#define STPMIC1_LDO12356_OUTPUT_MASK GENMASK(6, 2) +#define STPMIC1_LDO12356_OUTPUT_SHIFT 2 +#define STPMIC1_LDO3_MODE BIT(7) +#define STPMIC1_LDO3_DDR_SEL 31 +#define STPMIC1_LDO3_1800000 (9 << STPMIC1_LDO12356_OUTPUT_SHIFT) +#define STPMIC1_LDO4_UV 3300000 + +#define STPMIC1_USB_BOOST_EN BIT(0) +#define STPMIC1_USB_PWR_SW_EN GENMASK(2, 1) + +#define STPMIC1_NVM_USER_CONTROL_PROGRAM BIT(0) +#define STPMIC1_NVM_USER_CONTROL_READ BIT(1) + +#define STPMIC1_NVM_USER_STATUS_BUSY BIT(0) +#define STPMIC1_NVM_USER_STATUS_ERROR BIT(1) + +#define STPMIC1_DEFAULT_START_UP_DELAY_MS 1 +#define STPMIC1_DEFAULT_STOP_DELAY_MS 5 +#define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10 enum { - STPMU1_BUCK1, - STPMU1_BUCK2, - STPMU1_BUCK3, - STPMU1_BUCK4, - STPMU1_MAX_BUCK, + STPMIC1_BUCK1, + STPMIC1_BUCK2, + STPMIC1_BUCK3, + STPMIC1_BUCK4, + STPMIC1_MAX_BUCK, }; enum { - STPMU1_BUCK_MODE_HP, - STPMU1_BUCK_MODE_LP, + STPMIC1_BUCK_MODE_HP, + STPMIC1_BUCK_MODE_LP, }; enum { - STPMU1_LDO1, - STPMU1_LDO2, - STPMU1_LDO3, - STPMU1_LDO4, - STPMU1_LDO5, - STPMU1_LDO6, - STPMU1_MAX_LDO, + STPMIC1_LDO1, + STPMIC1_LDO2, + STPMIC1_LDO3, + STPMIC1_LDO4, + STPMIC1_LDO5, + STPMIC1_LDO6, + STPMIC1_MAX_LDO, }; enum { - STPMU1_LDO_MODE_NORMAL, - STPMU1_LDO_MODE_BYPASS, - STPMU1_LDO_MODE_SINK_SOURCE, + STPMIC1_LDO_MODE_NORMAL, + STPMIC1_LDO_MODE_BYPASS, + STPMIC1_LDO_MODE_SINK_SOURCE, }; enum { - STPMU1_PWR_SW1, - STPMU1_PWR_SW2, - STPMU1_MAX_PWR_SW, + STPMIC1_PWR_SW1, + STPMIC1_PWR_SW2, + STPMIC1_MAX_PWR_SW, }; - #endif |