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authorStefan Roese <sr@denx.de>2006-11-10 07:48:47 +0100
committerStefan Roese <sr@denx.de>2006-11-10 07:48:47 +0100
commitdfc8a9ee0040e53ada125a3c52f241e37f09cf28 (patch)
tree60fd3973150a4e6b3d9d129d117ecab71b5edabe /include/ppc440.h
parent5c912cb1c31266c66ca59b36f9b6f87296421d75 (diff)
parent91650b3e4de688038d4f71279c44858e3e2c6870 (diff)
Merge with /home/stefan/git/u-boot/denx
Diffstat (limited to 'include/ppc440.h')
-rw-r--r--include/ppc440.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/ppc440.h b/include/ppc440.h
index 0762e66301..407daaebe8 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1570,8 +1570,8 @@
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
#if defined(CONFIG_440GX)
-#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
-#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
+#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
+#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
#endif /* CONFIG_440GX */
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */