diff options
| author | Nikhil Badola <nikhil.badola@freescale.com> | 2014-04-07 08:46:14 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:49 -0700 |
| commit | 896720ceb2cededcd1f25fa5f5ff23822bea466d (patch) | |
| tree | 9394f32f5db254e5c438816c92f8bfc14bb35706 /include/usb | |
| parent | 55153d6c30d8ce11c8a7acf226375e61546b8401 (diff) | |
fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writes
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/usb')
| -rw-r--r-- | include/usb/ehci-fsl.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index 734305b9db..c9ee1d5bf6 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -164,6 +164,13 @@ #endif /* + * Increasing TX FIFO threshold value from 2 to 4 decreases + * data burst rate with which data packets are posted from the TX + * latency FIFO to compensate for latencies in DDR pipeline during DMA + */ +#define TXFIFOTHRESH 4 + +/* * USB Registers */ struct usb_ehci { |