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authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>2019-08-05 15:54:59 +0530
committerMichal Simek <michal.simek@xilinx.com>2019-10-08 09:11:14 +0200
commit26e054c943a7348904a8b432fc9a85185b0861c7 (patch)
treee9fe6b1ff6f4f9e1907df5390b59bf07fe983766 /include/xilinx.h
parent13210cd951046e828ecf3463f0087acbfb4f185e (diff)
arm64: versal: fpga: Add PL bit stream load support
This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'include/xilinx.h')
-rw-r--r--include/xilinx.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/xilinx.h b/include/xilinx.h
index af40befa52..ab4537becf 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -21,6 +21,7 @@ typedef enum { /* typedef xilinx_iface */
slave_selectmap, /* slave SelectMap (virtex2) */
devcfg, /* devcfg interface (zynq) */
csu_dma, /* csu_dma interface (zynqmp) */
+ cfi, /* CFI interface(versal) */
max_xilinx_iface_type /* insert all new types before this */
} xilinx_iface; /* end, typedef xilinx_iface */
@@ -32,6 +33,7 @@ typedef enum { /* typedef xilinx_family */
xilinx_spartan3, /* Spartan-III Family */
xilinx_zynq, /* Zynq Family */
xilinx_zynqmp, /* ZynqMP Family */
+ xilinx_versal, /* Versal Family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */