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| author | Tom Rini <trini@konsulko.com> | 2018-04-09 11:06:21 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-04-09 11:06:21 -0400 |
| commit | 2600df4f8ef12ece9cec13030005919e0ba2b0d5 (patch) | |
| tree | 993f32ce9c39fadc2effffb3690dc60cd1add303 /include/zynqmppl.h | |
| parent | 844fb498cc978608ec88bdf29913c0d46c85bfff (diff) | |
| parent | f190eaf002bf1434587d57c726b3dabfabbc8074 (diff) | |
Merge tag 'xilinx-for-v2018.05-rc2' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2018.05-rc2
- Various DT changes and sync with mainline kernel
- Various defconfig updates
- Add SPL init for zcu102 revA
- Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX
and zc1751-dc3
- Net fixes - xlnx,phy-type
- 64bit axi ethernet support
- arasan: Fix nand write issue
- fpga fixes
- Maintainer file updates
Diffstat (limited to 'include/zynqmppl.h')
| -rw-r--r-- | include/zynqmppl.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 4c8c2f88f0..8b3ce8ef77 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -12,6 +12,7 @@ #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 +#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017 #define ZYNQMP_FPGA_OP_INIT (1 << 0) #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) |