diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2018-01-16 20:44:25 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2018-01-19 17:59:35 +0300 |
| commit | 075cbae1639189a9d9c76e74e954721f354f397a (patch) | |
| tree | 7d10db927078e61b2b4b718ee18cdbc521b73e66 /include | |
| parent | 5aec2569a67f33c4ee58f7eb3a8a3d75751e3d49 (diff) | |
ARC: HSDK: CGU: Update AXI, TUN, ARC clock options
Update default AXI, TUN, ARC clock set options:
instead of changing only IDIV divider settings adjust also domain PLL
settings.
Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/snps,hsdk-cgu.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h b/include/dt-bindings/clock/snps,hsdk-cgu.h index 813ab71531..2cfe34eb35 100644 --- a/include/dt-bindings/clock/snps,hsdk-cgu.h +++ b/include/dt-bindings/clock/snps,hsdk-cgu.h @@ -33,8 +33,10 @@ #define CLK_SYS_UART_REF 18 #define CLK_SYS_EBI_REF 19 #define CLK_TUN_PLL 20 -#define CLK_TUN 21 -#define CLK_HDMI_PLL 22 -#define CLK_HDMI 23 +#define CLK_TUN_TUN 21 +#define CLK_TUN_ROM 22 +#define CLK_TUN_PWM 23 +#define CLK_HDMI_PLL 24 +#define CLK_HDMI 25 #endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */ |