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authorRobert Hancock <hancock@sedsystems.ca>2019-06-18 09:47:16 -0600
committerMichal Simek <michal.simek@xilinx.com>2019-07-30 10:20:06 +0200
commit175dccd710cc87f6046d91cc64896195e3b1edd5 (patch)
tree406e36d9a399cfe9ea3dd90ed2ed6575b1d9c3f9 /include
parenta0549f7390d33ec522de3a53e6031189d46a9ce7 (diff)
fpga: virtex2: Add slave serial programming support
This adds support for slave serial programming, in addition to the previously supported slave SelectMAP mode. There are two ways that this can be used: -Using the clk and wdata callbacks in order to write image data one bit at a time using pure bit-banging. This works, but is rather painfully slow with typical image sizes. -By specifying the wbulkdata callback instead, the image loading process can be offloaded to SPI hardware. In this mode the clk and wdata callbacks do not need to be specified. This allows the image to be loaded much faster, taking only a few seconds with even relatively large images. Slave serial programming has been tested on the Kintex-7 series of FPGAs. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'include')
-rw-r--r--include/virtex2.h13
1 files changed, 3 insertions, 10 deletions
diff --git a/include/virtex2.h b/include/virtex2.h
index a48113060e..7e8d93f24d 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -11,7 +11,7 @@
#include <xilinx.h>
/*
- * Slave SelectMap Implementation function table.
+ * Slave SelectMap or Serial Implementation function table.
*/
typedef struct {
xilinx_pre_fn pre;
@@ -24,18 +24,11 @@ typedef struct {
xilinx_wr_fn wr;
xilinx_rdata_fn rdata;
xilinx_wdata_fn wdata;
+ xilinx_bwr_fn wbulkdata;
xilinx_busy_fn busy;
xilinx_abort_fn abort;
xilinx_post_fn post;
-} xilinx_virtex2_slave_selectmap_fns;
-
-/* Slave Serial Implementation function table */
-typedef struct {
- xilinx_pgm_fn pgm;
- xilinx_clk_fn clk;
- xilinx_rdata_fn rdata;
- xilinx_wdata_fn wdata;
-} xilinx_virtex2_slave_serial_fns;
+} xilinx_virtex2_slave_fns;
#if defined(CONFIG_FPGA_VIRTEX2)
extern struct xilinx_fpga_op virtex2_op;