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authorTom Rini <trini@konsulko.com>2018-01-12 14:18:34 -0500
committerTom Rini <trini@konsulko.com>2018-01-12 14:18:34 -0500
commit18af965798153cea955773633feb05ed1647e9f6 (patch)
treea830ea881d8f1846cd5b25c0cce92756934d7139 /include
parentb6896fcbeb891b1e36c82e33e546e5ca277b8e52 (diff)
parent5fed97af20da955625cc06563a725b49cebb99eb (diff)
Merge git://git.denx.de/u-boot-tegra
Diffstat (limited to 'include')
-rw-r--r--include/configs/p2771-0000.h23
-rw-r--r--include/configs/tegra-common.h4
-rw-r--r--include/configs/tegra186-common.h10
-rw-r--r--include/configs/tegra210-common.h10
4 files changed, 27 insertions, 20 deletions
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
index 564069a665..29940a63de 100644
--- a/include/configs/p2771-0000.h
+++ b/include/configs/p2771-0000.h
@@ -24,9 +24,32 @@
/* PCI host support */
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
+ "ramdisk_addr_r\0" \
+ "kernel_addr_r_align=00200000\0" \
+ "kernel_addr_r_offset=00080000\0" \
+ "kernel_addr_r_size=02000000\0" \
+ "kernel_addr_r_aliases=loadaddr\0" \
+ "fdt_addr_r_align=00200000\0" \
+ "fdt_addr_r_offset=00000000\0" \
+ "fdt_addr_r_size=00200000\0" \
+ "scriptaddr_align=00200000\0" \
+ "scriptaddr_offset=00000000\0" \
+ "scriptaddr_size=00200000\0" \
+ "pxefile_addr_r_align=00200000\0" \
+ "pxefile_addr_r_offset=00000000\0" \
+ "pxefile_addr_r_size=00200000\0" \
+ "ramdisk_addr_r_align=00200000\0" \
+ "ramdisk_addr_r_offset=00000000\0" \
+ "ramdisk_addr_r_size=02000000\0"
+
#include "tegra-common-post.h"
/* Crystal is 38.4MHz. clk_m runs at half that rate */
#define COUNTER_FREQUENCY 19200000
+#undef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS (1024 + 2)
+
#endif
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 3cdd9741b2..2d98a6fa64 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -78,17 +78,21 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+#ifndef CONFIG_ARM64
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+#endif
+#ifndef CONFIG_ARM64
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
+#endif
/* Misc utility code */
#define CONFIG_BOUNCE_BUFFER
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
index 98e4fc2d25..1c8772a117 100644
--- a/include/configs/tegra186-common.h
+++ b/include/configs/tegra186-common.h
@@ -14,11 +14,6 @@
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_STACKBASE 0x82800000 /* 40MB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
@@ -60,9 +55,4 @@
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x80108000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
-#define CONFIG_SPL_STACK 0x800ffffc
-
#endif
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
index 4c05576a90..35735f3b78 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -15,11 +15,6 @@
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_STACKBASE 0x82800000 /* 40MB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
@@ -60,11 +55,6 @@
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x80108000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
-#define CONFIG_SPL_STACK 0x800ffffc
-
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10