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| author | Tom Rini <trini@konsulko.com> | 2019-03-10 10:16:07 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-03-10 10:16:07 -0400 |
| commit | 19c8c9c1031ebf345a68728d6f06d943207cea0f (patch) | |
| tree | 473081a243f14a82735242ef5e08cd9680a53a1d /include | |
| parent | bdbf50f80c72b81c37a4fcdce5a92b21b790f888 (diff) | |
| parent | 88c3bb49e1bf2b808cbad1fbdeda09480ae580a7 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Arria10 DRAM fixes and Gen5 cache fixes
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/socfpga_arria10_socdk.h | 2 | ||||
| -rw-r--r-- | include/configs/socfpga_common.h | 9 |
2 files changed, 8 insertions, 3 deletions
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 58e446b60a..0f116fbf2d 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -15,8 +15,6 @@ /* * U-Boot general configurations */ -/* Cache options */ -#define CONFIG_SYS_DCACHE_OFF /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c9cbf8f5e3..181af9b646 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -275,13 +275,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL QSPI boot support */ #ifdef CONFIG_SPL_SPI_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#endif #endif /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 +#endif #endif /* |