diff options
| author | Wolfgang Denk <wd@denx.de> | 2009-10-03 23:40:35 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-10-03 23:40:35 +0200 |
| commit | 311c19ccb5783a1de71fd5042eeadfbe9688f597 (patch) | |
| tree | 02b3d3c25b35eaba3373c1f9176f3b87bf48aec5 /include | |
| parent | eb4bf4c077dbf69a94a1697c784bc1f02aaab952 (diff) | |
| parent | 3b4bd2d75c4b3c1a4570f47ffaaed66f56a78ff4 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/ppc4xx-sdram.h | 7 | ||||
| -rw-r--r-- | include/configs/PMC440.h | 1 |
2 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index b6182d4f21..92be514b40 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -117,6 +117,7 @@ #define SDRAM_MCSTS_MRSC 0x80000000 #define SDRAM_MCSTS_SRMS 0x40000000 #define SDRAM_MCSTS_CIS 0x20000000 +#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */ /* * SDRAM Refresh Timer Register @@ -416,8 +417,7 @@ #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ #define SDRAM_MMODE 0x88 /* memory mode */ #define SDRAM_MEMODE 0x89 /* memory extended mode */ -#define SDRAM_ECCCR 0x98 /* ECC error status */ -#define SDRAM_ECCES SDRAM_ECCCR +#define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ #ifndef CONFIG_405EX #define SDRAM_RID 0xA8 /* revision ID */ @@ -1397,7 +1397,6 @@ /* * Prototypes */ -void inline blank_string(int size); inline void ppc4xx_ibm_ddr2_register_dump(void); u32 mfdcr_any(u32); void mtdcr_any(u32, u32); @@ -1405,6 +1404,8 @@ u32 ddr_wrdtr(u32); u32 ddr_clktr(u32); void spd_ddr_init_hang(void); u32 DQS_autocalibration(void); +phys_size_t sdram_memsize(void); +void dcbz_area(u32 start_address, u32 num_bytes); #endif /* __ASSEMBLY__ */ #endif /* _PPC4xx_SDRAM_H_ */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 012ae798d1..d6e2f6bc5e 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -215,7 +215,6 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif |