Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

22 files changed, 119 insertions, 18 deletions

diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index ff6624a227..b43dba3352 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -52,9 +52,7 @@ typedef	struct	global_data {
 	unsigned long	scc_clk;
 	unsigned long	brg_clk;
 #endif
-#if defined(CONFIG_MPC7448HPC2)
 	unsigned long   mem_clk;
-#endif
 #if defined(CONFIG_MPC83XX)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index d769d70120..3506aec5ec 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -57,7 +57,7 @@ typedef struct ccsr_local_ecm {
 	uint	lawbar7;	/* 0xce8 - Local Access Window 7 Base Address Register */
 	char	res19[4];
 	uint	lawar7;		/* 0xcf0 - Local Access Window 7 Attributes Register */
-	char	res20[780];
+	char	res20[780];		// XXX: LAW 8, LAW9 for 8572
 	uint	eebacr;		/* 0x1000 - ECM CCB Address Configuration Register */
 	char	res21[12];
 	uint	eebpcr;		/* 0x1010 - ECM CCB Port Configuration Register */
@@ -86,7 +86,12 @@ typedef struct ccsr_ddr {
 	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
 	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
 	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
-	char	res5[112];
+	char	res4a[48];
+	uint	cs0_config_2;		/* 0x20c0 - DDR Chip Select Configuration 2 */
+	uint	cs1_config_2;		/* 0x20c4 - DDR Chip Select Configuration 2 */
+	uint	cs2_config_2;		/* 0x20c8 - DDR Chip Select Configuration 2 */
+	uint	cs3_config_2;		/* 0x20cc - DDR Chip Select Configuration 2 */
+	char	res5[48];
 	uint	ext_refrec;		/* 0x2100 - DDR SDRAM Extended Refresh Recovery */
 	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
@@ -103,7 +108,17 @@ typedef struct ccsr_ddr {
 	char	res7[20];
 	uint	init_address;		/* 0x2148 - DDR training initialization address */
 	uint	init_ext_address;	/* 0x214C - DDR training initialization extended address */
-	char	res8_1[2728];
+	char	res8_1[16];
+	uint	timing_cfg_4;		/* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
+	uint	timing_cfg_5;		/* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
+	char	reg8_1a[8];
+	uint	ddr_zq_cntl;		/* 0x2170 - DDR ZQ calibration control*/
+	uint	ddr_wrlvl_cntl;		/* 0x2174 - DDR write leveling control*/
+	uint	ddr_pd_cntl;		/* 0x2178 - DDR pre-drive conditioning control*/
+	uint	ddr_sr_cntr;		/* 0x217C - DDR self refresh counter */
+	uint	ddr_sdram_rcw_1;	/* 0x2180 - DDR Register Control Words 1 */
+	uint	ddr_sdram_rcw_2;	/* 0x2184 - DDR Register Control Words 2 */
+	char	res8_1b[2672];
 	uint	ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
 	uint	ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
 	char	res8_2[512];
@@ -217,7 +232,7 @@ typedef struct ccsr_lbc {
 	char	res7[12];
 	uint	lbcr;		/* 0x50d0 - LBC Configuration Register */
 	uint	lcrr;		/* 0x50d4 - LBC Clock Ratio Register */
-	char	res8[12072];
+	char	res8[3880];
 } ccsr_lbc_t;
 
 /*
@@ -1578,7 +1593,11 @@ typedef struct ccsr_gur {
 #define MPC85xx_DEVDISR_RMSG		0x00040000
 #define MPC85xx_DEVDISR_DDR 		0x00010000
 #define MPC85xx_DEVDISR_CPU 		0x00008000
+#define MPC85xx_DEVDISR_CPU0 		MPC85xx_DEVDISR_CPU
 #define MPC85xx_DEVDISR_TB 		0x00004000
+#define MPC85xx_DEVDISR_TB0 		MPC85xx_DEVDISR_TB
+#define MPC85xx_DEVDISR_CPU1 		0x00002000
+#define MPC85xx_DEVDISR_TB1 		0x00001000
 #define MPC85xx_DEVDISR_DMA		0x00000400
 #define MPC85xx_DEVDISR_TSEC1		0x00000080
 #define MPC85xx_DEVDISR_TSEC2		0x00000040
@@ -1624,6 +1643,8 @@ typedef struct ccsr_gur {
 #define CFG_MPC85xx_ECM_ADDR	(CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
 #define CFG_MPC85xx_DDR_OFFSET	(0x2000)
 #define CFG_MPC85xx_DDR_ADDR	(CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
+#define CFG_MPC85xx_DDR2_OFFSET	(0x6000)
+#define CFG_MPC85xx_DDR2_ADDR	(CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET)
 #define CFG_MPC85xx_LBC_OFFSET	(0x5000)
 #define CFG_MPC85xx_LBC_ADDR	(CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
 #define CFG_MPC85xx_PCIX_OFFSET	(0x8000)
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index b7a5b28806..544cc010db 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -879,22 +879,42 @@
 #define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
 #define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
 
+/* Some parts define SVR[0:23] as the SOC version */
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF)	/* SOC Version fields */
+
 
 /*
- * SVR_VER() Version Values
+ * SVR_SOC_VER() Version Values
  */
 
-#define SVR_8540	0x8030
-#define SVR_8560	0x8070
-#define SVR_8555	0x8079
-#define SVR_8541	0x807A
-#define SVR_8544	0x8034
-#define SVR_8544_E	0x803C
-#define SVR_8548	0x8031
-#define SVR_8548_E	0x8039
-#define SVR_8610	0x80A0
-#define SVR_8641	0x8090
-#define SVR_8568_E	0x807D
+#define SVR_8533	0x803400
+#define SVR_8533_E	0x803C00
+#define SVR_8540	0x803000
+#define SVR_8541	0x807200
+#define SVR_8541_E	0x807A00
+#define SVR_8543	0x803200
+#define SVR_8543_E	0x803A00
+#define SVR_8544	0x803401
+#define SVR_8544_E	0x803C01
+#define SVR_8545	0x803102
+#define SVR_8545_E	0x803902
+#define SVR_8547_E	0x803901
+#define SVR_8548	0x803100
+#define SVR_8548_E	0x803900
+#define SVR_8555	0x807100
+#define SVR_8555_E	0x807900
+#define SVR_8560	0x807000
+#define SVR_8567	0x807600
+#define SVR_8567_E	0x807E00
+#define SVR_8568	0x807500
+#define SVR_8568_E	0x807D00
+#define SVR_8572	0x80E000
+#define SVR_8572_E	0x80E800
+
+#define SVR_8610	0x80A000
+#define SVR_8641	0x809000
+#define SVR_8641D	0x809001
+
 
 
 /* I am just adding a single entry for 8260 boards.  I think we may be
diff --git a/include/common.h b/include/common.h
index e03ead10bc..39bcd307b5 100644
--- a/include/common.h
+++ b/include/common.h
@@ -669,4 +669,11 @@ void inline show_boot_progress (int val);
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 
+/* Multicore arch functions */
+#ifdef CONFIG_MP
+int cpu_status(int nr);
+int cpu_reset(int nr);
+int cpu_release(int nr, int argc, char *argv[]);
+#endif
+
 #endif	/* __COMMON_H_ */
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index c14376e7f4..0d644da7ae 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -96,6 +96,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define PCI_SPEED		33333000        /* CPLD currenlty does not have PCI setup info */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5ea7b25047..85934d718d 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -100,6 +100,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 174215c2cc..77eea73787 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -83,6 +83,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR 	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 7334088b18..3f3f741ade 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -49,6 +49,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
@@ -82,6 +85,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 /*
@@ -273,6 +277,8 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM   0xf8000801
 #define CFG_OR3_PRELIM   0xfff00ff7
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index a8942095c9..c83d9e25d9 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -98,6 +98,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index a3db9f4457..fc8ad8813f 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -57,6 +57,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
@@ -96,6 +99,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
@@ -296,6 +300,8 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM	 0xf8000801
 #define CFG_OR3_PRELIM	 0xfff00ff7
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 93877aedb0..500b57cece 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -49,6 +49,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
@@ -82,6 +85,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 /*
@@ -273,6 +277,8 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM   0xf8000801
 #define CFG_OR3_PRELIM   0xfff00ff7
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 08884b36f0..e30302c5d4 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -95,6 +95,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index a12d193c71..7bb20e58ca 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -90,6 +90,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 819bee70a1..bd058fc155 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -92,6 +92,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 8902f42ff1..38a26dc8aa 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -94,6 +94,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 2bbfe9aa62..946b3c2d8a 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -99,6 +99,7 @@
 #else
   #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
 #endif
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 21e8bafc2c..fca5f74df7 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -89,6 +89,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
 #define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 /*
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 516203a5d8..49a72347fb 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -87,6 +87,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index f9ede5f187..81a1e072c6 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -93,6 +93,7 @@
 #else
   #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
 #endif
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 047e1cf99a..fc5d0cc76a 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -114,6 +114,7 @@
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
 #endif
 #define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index e09dd7163f..15f690af16 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -127,6 +127,7 @@
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
 #endif
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 3b10452416..b0c1957aea 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2050,3 +2050,26 @@
 #define PCI_DEVICE_ID_MICROGATE_USC	0x0010
 #define PCI_DEVICE_ID_MICROGATE_SCC	0x0020
 #define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
+
+#define PCI_VENDOR_ID_FREESCALE		0x1957
+#define PCI_DEVICE_ID_MPC8548E		0x0012
+#define PCI_DEVICE_ID_MPC8548		0x0013
+#define PCI_DEVICE_ID_MPC8543E		0x0014
+#define PCI_DEVICE_ID_MPC8543		0x0015
+#define PCI_DEVICE_ID_MPC8547E		0x0018
+#define PCI_DEVICE_ID_MPC8545E		0x0019
+#define PCI_DEVICE_ID_MPC8545		0x001a
+#define PCI_DEVICE_ID_MPC8568E		0x0020
+#define PCI_DEVICE_ID_MPC8568		0x0021
+#define PCI_DEVICE_ID_MPC8567E		0x0022
+#define PCI_DEVICE_ID_MPC8567		0x0023
+#define PCI_DEVICE_ID_MPC8533E		0x0030
+#define PCI_DEVICE_ID_MPC8533		0x0031
+#define PCI_DEVICE_ID_MPC8544E		0x0032
+#define PCI_DEVICE_ID_MPC8544		0x0033
+#define PCI_DEVICE_ID_MPC8572E		0x0040
+#define PCI_DEVICE_ID_MPC8572		0x0041
+#define PCI_DEVICE_ID_MPC8641		0x7010
+#define PCI_DEVICE_ID_MPC8641D		0x7011
+#define PCI_DEVICE_ID_MPC8610		0x7018
+