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authorLokesh Vutla <lokeshvutla@ti.com>2017-05-05 12:59:08 +0530
committerTom Rini <trini@konsulko.com>2017-05-12 08:37:12 -0400
commit59041a508429f1cfa12774c2f226a27f6344330b (patch)
tree8cf6f36f224d1be57b642e05dbe9301eb8153ec7 /include
parentc187dd685adcbfd24b119e3a50a96132bdad1639 (diff)
arm: am33xx: Fix MPU opp selection
Update MPU frequencies and voltages as per the latest DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4. Below is the consolidated data: MPU values for PG 2.0 and later(Package ZCZ and ZCE): ------------------------------------------------------- | | ZCZ | ZCE | |-------------------------------------------------------| | | VDD[V] | ARM [MHz] | VDD[V] | ARM [MHz] | |-------|----------|------------|----------|------------| | NITRO | 1.325 | 1000 | NA | NA | |-------|----------|------------|----------|------------| | TURBO | 1.26 | 800 | NA | NA | |-------|----------|------------|----------|------------| |OPP120 | 1.20 | 720 | NA | NA | |-------|----------|------------|----------|------------| |OPP100 | 1.10 | 600 | 1.10 | 600 | |-------|----------|------------|----------|------------| | OPP50 | 0.95 | 300 | 0.95 | 300 | ------------------------------------------------------- There is no eFuse blown on PG1.0 Silicons due to which there is no way to detect the maximum frequencies supported. So default to OPP100 for which both frequency and voltages are common on both the packages. [1] http://www.ti.com/lit/ds/symlink/am3356.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include')
-rw-r--r--include/power/tps65910.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/power/tps65910.h b/include/power/tps65910.h
index ca8430145b..976130dc3e 100644
--- a/include/power/tps65910.h
+++ b/include/power/tps65910.h
@@ -62,6 +62,7 @@ enum {
#define TPS65910_OP_REG_SEL_MASK (0x7F)
#define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */
+#define TPS65910_OP_REG_SEL_1_1_0 (0x2B) /* 1.1000 V */
#define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */
#define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */
#define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */