summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorWolfgang Denk <wd@denx.de>2008-12-05 00:17:16 +0100
committerWolfgang Denk <wd@denx.de>2008-12-05 00:17:16 +0100
commit762bd90cbb6536d2c8451c13fe23552f3311f860 (patch)
tree12421c51ac7f71f6e1591a60e81988fe06777304 /include
parent6226db68af76bec165bfdfd04ef52d9a54345917 (diff)
parentdc889e865356497d3e495570118c2245ebce2631 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/fsl_lbc.h8
-rw-r--r--include/asm-ppc/immap_85xx.h3
-rw-r--r--include/configs/MPC8536DS.h2
-rw-r--r--include/configs/MPC8544DS.h2
-rw-r--r--include/configs/MPC8548CDS.h2
-rw-r--r--include/configs/MPC8568MDS.h2
-rw-r--r--include/configs/MPC8572DS.h27
-rw-r--r--include/configs/MPC8641HPCN.h9
8 files changed, 27 insertions, 28 deletions
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index cac7bf6bf5..51fc5c13b0 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -69,6 +69,14 @@
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
#endif
+/* Convert an address into the right format for the BR registers */
+#ifdef CONFIG_PHYS_64BIT
+#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
+ ((x & 0x300000000ULL) >> 19)))
+#else
+#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
+
/* OR - Option Registers
*/
#define OR0 0x5004 /* Register offset to immr */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 75b451d201..e5046bef32 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1569,6 +1569,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
+#define MPC85xx_PORDEVSR_PCI1 0x00800000
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
@@ -1647,8 +1648,6 @@ typedef struct ccsr_gur {
char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
-#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
-
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index f3eee23aa1..5a99d5fe79 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -99,7 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_DDR_SPD
#undef CONFIG_DDR_DLL
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index ff24fa50eb..b31c2bb371 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -97,7 +97,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 62955909e7..7a7e5a1457 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -100,7 +100,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_DDR_SPD
#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 9e16bb451f..8bdec65b7c 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -92,7 +92,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 9f01f9aaa8..9a66ca8102 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -99,6 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_DDR_SPD
#undef CONFIG_DDR_DLL
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
@@ -114,22 +115,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
+#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0 0x00260802
+#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
+#define CONFIG_SYS_DDR_MODE_1 0x00440462
#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06180100
+#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
+#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400010
+#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2 0x24400000
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index cd9889495d..5a832961c2 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -186,17 +186,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
| CONFIG_SYS_PHYS_ADDR_HIGH)
-
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-/* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
-#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
- ((x & 0x300000000ULL) >> 19)))
-#else
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
-#endif
-
#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
| 0x00001001) /* port size 16bit */
#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/