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authorHannes Schmelzer <oe5hpm@oevsv.at>2018-03-07 08:00:56 +0100
committerJaehoon Chung <jh80.chung@samsung.com>2018-05-02 10:57:43 +0900
commit88a57125fa689f3207c5409ef6eeb6a47ff051cd (patch)
tree469223617898f0bc0038045be3db354ad784bfcc /include
parent0a4c2b099ed44a18c7768001cb974e80bff0f46b (diff)
mmc: sdhci: add SDHCI_QUIRK_BROKEN_HISPD_MODE
Some IP-core implementations of the SDHCI have different troubles on the silicon where they are placed. On ZYNQ platform for example Xilinx doesn't accept the hold timing of an eMMC chip which operates in High-Speed mode and must be forced to operate in non high-speed mode. To get rid of this "SDHCI_QUIRK_BROKEN_HISPD_MODE" is introduced. For more details about this refer to the Xilinx answer-recor #59999 https://www.xilinx.com/support/answers/59999.html This commit: - doesn't set HISPD bit on the host-conroller - reflects this fact within the host-controller capabilities Upon this the layer above (mmc-driver) can setup the card correctly. Otherwise the MMC card will be switched into high-speed mode and causes possible timing violation on the host-controller side. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Diffstat (limited to 'include')
-rw-r--r--include/sdhci.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/sdhci.h b/include/sdhci.h
index 7e84012f60..ed35f0434a 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -213,6 +213,12 @@
#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
+/*
+ * SDHCI_QUIRK_BROKEN_HISPD_MODE
+ * the hardware cannot operate correctly in high-speed mode,
+ * this quirk forces the sdhci host-controller to non high-speed mode
+ */
+#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)