diff options
| author | Stefan Roese <sr@denx.de> | 2009-07-29 08:45:27 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-07-30 07:22:18 +0200 |
| commit | 89bcc4875007ef6608297dc11e7a0d1fbd9900d2 (patch) | |
| tree | 3330e8033d634b70de6298ab20bd2468b4462528 /include | |
| parent | 82a7edc7ea8f5fe55fed4ff7e127469569e539c4 (diff) | |
ppc4xx: Add basic support for AMCC PPC460EX/460GT rev B chips
This patch is based on a diff created by Phong Vo from AMCC.
Signed-off-by: Phong Vo <pvo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/processor.h | 2 | ||||
| -rw-r--r-- | include/ppc440.h | 5 |
2 files changed, 7 insertions, 0 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 2c0c0cee40..2841104515 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -883,8 +883,10 @@ #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ #define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ +#define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/ #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/ #define PVR_460SX_RA 0x13541800 /* 460SX rev A */ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ diff --git a/include/ppc440.h b/include/ppc440.h index 6ce53a6ef2..e6dc7406f4 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1156,6 +1156,11 @@ #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + /* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */ #define SDR0_ETH_PLL 0x4102 #define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/ |