diff options
| author | Wolfgang Denk <wd@denx.de> | 2010-01-27 20:19:08 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-01-27 20:19:08 +0100 |
| commit | 9b208ece0a4e040774e24990b7cb6f0ad0ca4cc7 (patch) | |
| tree | ca54c5529ccfab941f6cb20048453c5802440e77 /include | |
| parent | 249d4dec69e8d41ca58fe6cb3c56ea6f0480ef16 (diff) | |
| parent | a9c3ac78d81d7ff4fe239e292e11e0f78ac5d461 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/immap_86xx.h | 33 | ||||
| -rw-r--r-- | include/common.h | 1 |
2 files changed, 19 insertions, 15 deletions
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 098f25384b..fd7acdb767 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1186,17 +1186,8 @@ typedef struct ccsr_rio { typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */ -#define MPC8610_PORBMSR_HA 0x00070000 -#define MPC8610_PORBMSR_HA_SHIFT 16 -#define MPC8641_PORBMSR_HA 0x00060000 -#define MPC8641_PORBMSR_HA_SHIFT 17 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ -#define MPC8610_PORDEVSR_IO_SEL 0x00380000 -#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19 -#define MPC8641_PORDEVSR_IO_SEL 0x000F0000 -#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16 -#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */ uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ char res1[12]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ @@ -1210,11 +1201,6 @@ typedef struct ccsr_gur { uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ -#define MPC86xx_DEVDISR_PCIEX1 0x80000000 -#define MPC86xx_DEVDISR_PCIEX2 0x40000000 -#define MPC86xx_DEVDISR_PCI1 0x80000000 -#define MPC86xx_DEVDISR_PCIE1 0x40000000 -#define MPC86xx_DEVDISR_PCIE2 0x20000000 char res7[12]; uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; @@ -1225,7 +1211,6 @@ typedef struct ccsr_gur { uint svr; /* 0xe00a4 - System version register */ char res10a[8]; uint rstcr; /* 0xe00b0 - Reset control register */ -#define MPC86xx_RSTCR_HRST_REQ 0x00000002 char res10b[1868]; uint clkdvdr; /* 0xe0800 - Clock Divide register */ char res10c[796]; @@ -1250,6 +1235,24 @@ typedef struct ccsr_gur { char res16[184]; } ccsr_gur_t; +#define MPC8610_PORBMSR_HA 0x00070000 +#define MPC8610_PORBMSR_HA_SHIFT 16 +#define MPC8641_PORBMSR_HA 0x00060000 +#define MPC8641_PORBMSR_HA_SHIFT 17 +#define MPC8610_PORDEVSR_IO_SEL 0x00380000 +#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19 +#define MPC8641_PORDEVSR_IO_SEL 0x000F0000 +#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16 +#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */ +#define MPC86xx_DEVDISR_PCIEX1 0x80000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 +#define MPC86xx_DEVDISR_PCI1 0x80000000 +#define MPC86xx_DEVDISR_PCIE1 0x40000000 +#define MPC86xx_DEVDISR_PCIE2 0x20000000 +#define MPC86xx_DEVDISR_CPU0 0x00008000 +#define MPC86xx_DEVDISR_CPU1 0x00004000 +#define MPC86xx_RSTCR_HRST_REQ 0x00000002 + /* * Watchdog register block(0xe_4000-0xe_4fff) */ diff --git a/include/common.h b/include/common.h index 391790a411..81f2b59dea 100644 --- a/include/common.h +++ b/include/common.h @@ -712,6 +712,7 @@ void show_boot_progress(int val); #ifdef CONFIG_MP int cpu_status(int nr); int cpu_reset(int nr); +int cpu_disable(int nr); int cpu_release(int nr, int argc, char *argv[]); #endif |