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authorEzequiel Garcia <ezequiel@vanguardiasur.com.ar>2018-01-12 12:33:50 -0300
committerMichal Simek <michal.simek@xilinx.com>2018-05-31 13:50:39 +0200
commitc66f5620e6a63b1912c017781c7eec6400dde292 (patch)
treec4518dca9dbc111466d436bddaca765b9f812651 /include
parent5dd84a3fbd18bb16520d8ce35183b7fa2fe10d37 (diff)
arm: zynq: Add support for Bitmain Antminer S9 control board
This is control board on Bitmain Antminer S9. There are 3 board variables with 256MB, 512MB and 1024MB DDR. DDR memory is automatically detected with using get_with using get_ram_size(). Bitmain is using 16MB space for FPGA which is handled via reserved-memory. Also U-Boot is allocating 16B for storing bootcounts. Watchdog is started but never service in U-Boot. SPL MMC is working. SPL NAND is not working because it is not supported as of now. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/bitmain_antminer_s9.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h
new file mode 100644
index 0000000000..226750215e
--- /dev/null
+++ b/include/configs/bitmain_antminer_s9.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2018 Michal Simek <monstr@monstr.eu>
+ */
+
+#ifndef __CONFIG_BITMAIN_ANTMINER_S9_H
+#define __CONFIG_BITMAIN_ANTMINER_S9_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0x300000
+
+#define CONFIG_BOOTP_SERVERIP
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=no\0" \
+ "pxefile_addr_r=0x2000000\0" \
+ "scriptaddr=0x3000000\0" \
+ "kernel_addr_r=0x2000000\0" \
+ "fdt_high=0xefff000\0" \
+ "initrd_high=0xefff000\0" \
+ "devnum=0\0" \
+ "wdstop=mw f8005000 ABC000\0" \
+ BOOTENV
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_BITMAIN_ANTMINER_S9_H */