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authorTom Rini <trini@konsulko.com>2018-06-15 09:38:06 -0400
committerTom Rini <trini@konsulko.com>2018-06-15 09:38:06 -0400
commitd94e89c7650f496ce1e9303093c1e2d268d91b1b (patch)
tree36e556587e05858de00cc837f98122d80bdecf1f /include
parent9d0dc69235e8327dba5536761c768d40c4e514e5 (diff)
parentb729ed0d95415bd694a6b67c0761f03ef5a1e2bc (diff)
Merge tag 'xilinx-for-v2018.07-rc2' of git://git.denx.de/u-boot-microblaze
Xilinx fixes for v2018.07-rc2 Zynq: - Fix missing watchdog header - DT fixes ZynqMP: - emmc configuration split - Enable SPD - Fix PMUFW_INIT_FILE logic - Coverity fixes in SoC code timer - Add timer_get_boot_us mmc: - Fix MMC HS200 tuning command serial: - Fix scrabled chars with OF_LIVE
Diffstat (limited to 'include')
-rw-r--r--include/configs/xilinx_zynqmp_zcu102.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index ca11b97c7c..ad6bc3d1bf 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -39,6 +39,9 @@
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
+#define CONFIG_SPD_EEPROM
+#define CONFIG_DDR_SPD
+
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZCU102_H */