Merge branch '2020-01-15-master-imports'

- MediaTek improvements
- Some generic clk improvements
- A few assorted bugfixes

7 files changed, 627 insertions, 0 deletions

diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 296c0cf9b8..17a31ec788 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -8,6 +8,8 @@
 #ifndef _ASM_GENERIC_SECTIONS_H_
 #define _ASM_GENERIC_SECTIONS_H_
 
+#include <linux/types.h>
+
 /* References to section boundaries */
 
 extern char _text[], _stext[], _etext[];
diff --git a/include/clk.h b/include/clk.h
index a5ee53d94a..3336301815 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -155,6 +155,34 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk);
 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk);
 
 /**
+ * clk_get_by_name_nodev - Get/request a clock by name without a device.
+ *
+ * This is a version of clk_get_by_name() that does not use a device.
+ *
+ * @node:	The client ofnode.
+ * @name:	The name of the clock to request, within the client's list of
+ *		clocks.
+ * @clock:	A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk);
+
+/**
+ * clock_get_optional_nodev - Get/request an optinonal clock by name
+ *		without a device.
+ * @node:	The client ofnode.
+ * @name:	The name of the clock to request.
+ * @name:	The name of the clock to request, within the client's list of
+ *		clocks.
+ * @clock:	A pointer to a clock struct to initialize.
+ *
+ * Behaves the same as clk_get_by_name_nodev() except where there is
+ * no clock producer, in this case, skip the error number -ENODATA, and
+ * the function returns 0.
+ */
+int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk);
+
+/**
  * devm_clk_get - lookup and obtain a managed reference to a clock producer.
  * @dev: device for clock "consumer"
  * @id: clock consumer ID
@@ -230,6 +258,18 @@ static inline int clk_get_by_name(struct udevice *dev, const char *name,
 	return -ENOSYS;
 }
 
+static inline int
+clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
+{
+	return -ENOSYS;
+}
+
+static inline int
+clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
+{
+	return -ENOSYS;
+}
+
 static inline int clk_release_all(struct clk *clk, int count)
 {
 	return -ENOSYS;
diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h
new file mode 100644
index 0000000000..dfd506ed24
--- /dev/null
+++ b/include/configs/mt7622.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7629 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#ifndef __MT7622_H
+#define __MT7622_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_MAXARGS		8
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+#define CONFIG_SYS_CBSIZE		SZ_1K
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +	\
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M
+#define CONFIG_SYS_NONCACHED_MEMORY	SZ_1M
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* Uboot definition */
+#define CONFIG_SYS_UBOOT_BASE                   CONFIG_SYS_TEXT_BASE
+
+/* SPL -> Uboot */
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_2M - \
+					 GENERATED_GBL_DATA_SIZE)
+/* UBoot -> Kernel */
+#define CONFIG_LOADADDR		        0x4007ff28
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* DRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/* Ethernet */
+#define CONFIG_IPADDR			192.168.1.1
+#define CONFIG_SERVERIP			192.168.1.3
+
+#endif
diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h
new file mode 100644
index 0000000000..253a54332c
--- /dev/null
+++ b/include/configs/mt8512.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT8512 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#ifndef __MT8512_H
+#define __MT8512_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_NONCACHED_MEMORY		SZ_1M
+
+#define CONFIG_CPU_ARMV8
+
+#define COUNTER_FREQUENCY			13000000
+
+#define CONFIG_SYS_LOAD_ADDR			0x41000000
+#define CONFIG_LOADADDR				CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_MALLOC_LEN			SZ_32M
+#define CONFIG_SYS_BOOTM_LEN			SZ_64M
+
+/* Uboot definition */
+#define CONFIG_SYS_UBOOT_START			CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR			(CONFIG_SYS_TEXT_BASE + \
+						SZ_2M - \
+						GENERATED_GBL_DATA_SIZE)
+
+/* ENV Setting */
+#if defined(CONFIG_MMC_MTK)
+#define CONFIG_SYS_MMC_ENV_DEV			0
+#define CONFIG_ENV_OVERWRITE
+
+/* MMC offset in block unit,and block size is 0x200 */
+#define ENV_BOOT_READ_IMAGE \
+	"boot_rd_img=mmc dev 0" \
+	";mmc read ${loadaddr} 0x27000 0x8000" \
+	";iminfo ${loadaddr}\0"
+#endif
+
+/* Console configuration */
+#define ENV_DEVICE_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+
+#define ENV_BOOT_CMD \
+	"mtk_boot=run boot_rd_img;bootm;\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0x6c000000\0" \
+	ENV_DEVICE_SETTINGS \
+	ENV_BOOT_READ_IMAGE \
+	ENV_BOOT_CMD \
+	"bootcmd=run mtk_boot;\0" \
+
+#endif
diff --git a/include/dma.h b/include/dma.h
index 6c55aa3a00..5b247b5b06 100644
--- a/include/dma.h
+++ b/include/dma.h
@@ -304,6 +304,7 @@ int dma_send(struct dma *dma, void *src, size_t len, void *metadata);
 int dma_get_cfg(struct dma *dma, u32 cfg_id, void **cfg_data);
 #endif /* CONFIG_DMA_CHANNELS */
 
+#if CONFIG_IS_ENABLED(DMA)
 /*
  * dma_get_device - get a DMA device which supports transfer
  * type of transfer_type
@@ -327,5 +328,15 @@ int dma_get_device(u32 transfer_type, struct udevice **devp);
 	     transferred and on failure return error code.
  */
 int dma_memcpy(void *dst, void *src, size_t len);
+#else
+static inline int dma_get_device(u32 transfer_type, struct udevice **devp)
+{
+	return -ENOSYS;
+}
 
+static inline int dma_memcpy(void *dst, void *src, size_t len)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_DMA */
 #endif	/* _DMA_H_ */
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
new file mode 100644
index 0000000000..22b8d08b60
--- /dev/null
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef _DT_BINDINGS_CLK_MT7622_H
+#define _DT_BINDINGS_CLK_MT7622_H
+
+/* TOPCKGEN */
+
+/* FIXED_CLKS */
+#define CLK_TOP_TO_U2_PHY		0
+#define CLK_TOP_TO_U2_PHY_1P		1
+#define CLK_TOP_PCIE0_PIPE_EN		2
+#define CLK_TOP_PCIE1_PIPE_EN		3
+#define CLK_TOP_SSUSB_TX250M		4
+#define CLK_TOP_SSUSB_EQ_RX250M		5
+#define CLK_TOP_SSUSB_CDR_REF		6
+#define CLK_TOP_SSUSB_CDR_FB		7
+#define CLK_TOP_SATA_ASIC		8
+#define CLK_TOP_SATA_RBC		9
+/* FIXED_DIVS */
+#define CLK_TOP_TO_USB3_SYS		10
+#define CLK_TOP_P1_1MHZ			11
+#define CLK_TOP_4MHZ			12
+#define CLK_TOP_P0_1MHZ			13
+#define CLK_TOP_TXCLK_SRC_PRE		14
+#define CLK_TOP_RTC			15
+#define CLK_TOP_MEMPLL			16
+#define CLK_TOP_DMPLL			17
+#define CLK_TOP_SYSPLL_D2		18
+#define CLK_TOP_SYSPLL1_D2		19
+#define CLK_TOP_SYSPLL1_D4		20
+#define CLK_TOP_SYSPLL1_D8		21
+#define CLK_TOP_SYSPLL2_D4		22
+#define CLK_TOP_SYSPLL2_D8		23
+#define CLK_TOP_SYSPLL_D5		24
+#define CLK_TOP_SYSPLL3_D2		25
+#define CLK_TOP_SYSPLL3_D4		26
+#define CLK_TOP_SYSPLL4_D2		27
+#define CLK_TOP_SYSPLL4_D4		28
+#define CLK_TOP_SYSPLL4_D16		29
+#define CLK_TOP_UNIVPLL			30
+#define CLK_TOP_UNIVPLL_D2		31
+#define CLK_TOP_UNIVPLL1_D2		32
+#define CLK_TOP_UNIVPLL1_D4		33
+#define CLK_TOP_UNIVPLL1_D8		34
+#define CLK_TOP_UNIVPLL1_D16		35
+#define CLK_TOP_UNIVPLL2_D2		36
+#define CLK_TOP_UNIVPLL2_D4		37
+#define CLK_TOP_UNIVPLL2_D8		38
+#define CLK_TOP_UNIVPLL2_D16		39
+#define CLK_TOP_UNIVPLL_D5		40
+#define CLK_TOP_UNIVPLL3_D2		41
+#define CLK_TOP_UNIVPLL3_D4		42
+#define CLK_TOP_UNIVPLL3_D16		43
+#define CLK_TOP_UNIVPLL_D7		44
+#define CLK_TOP_UNIVPLL_D80_D4		45
+#define CLK_TOP_UNIV48M			46
+#define CLK_TOP_SGMIIPLL		47
+#define CLK_TOP_SGMIIPLL_D2		48
+#define CLK_TOP_AUD1PLL			49
+#define CLK_TOP_AUD2PLL			50
+#define CLK_TOP_AUD_I2S2_MCK		51
+#define CLK_TOP_TO_USB3_REF		52
+#define CLK_TOP_PCIE1_MAC_EN		53
+#define CLK_TOP_PCIE0_MAC_EN		54
+#define CLK_TOP_ETH_500M		55
+/* TOP_MUXES */
+#define CLK_TOP_AXI_SEL			56
+#define CLK_TOP_MEM_SEL			57
+#define CLK_TOP_DDRPHYCFG_SEL		58
+#define CLK_TOP_ETH_SEL			59
+#define CLK_TOP_PWM_SEL			60
+#define CLK_TOP_F10M_REF_SEL		61
+#define CLK_TOP_NFI_INFRA_SEL		62
+#define CLK_TOP_FLASH_SEL		63
+#define CLK_TOP_UART_SEL		64
+#define CLK_TOP_SPI0_SEL		65
+#define CLK_TOP_SPI1_SEL		66
+#define CLK_TOP_MSDC50_0_SEL		67
+#define CLK_TOP_MSDC30_0_SEL		68
+#define CLK_TOP_MSDC30_1_SEL		69
+#define CLK_TOP_A1SYS_HP_SEL		70
+#define CLK_TOP_A2SYS_HP_SEL		71
+#define CLK_TOP_INTDIR_SEL		72
+#define CLK_TOP_AUD_INTBUS_SEL		73
+#define CLK_TOP_PMICSPI_SEL		74
+#define CLK_TOP_SCP_SEL			75
+#define CLK_TOP_ATB_SEL			76
+#define CLK_TOP_HIF_SEL			77
+#define CLK_TOP_AUDIO_SEL		78
+#define CLK_TOP_U2_SEL			79
+#define CLK_TOP_AUD1_SEL		80
+#define CLK_TOP_AUD2_SEL		81
+#define CLK_TOP_IRRX_SEL		82
+#define CLK_TOP_IRTX_SEL		83
+#define CLK_TOP_ASM_L_SEL		84
+#define CLK_TOP_ASM_M_SEL		85
+#define CLK_TOP_ASM_H_SEL		86
+#define CLK_TOP_APLL1_SEL		87
+#define CLK_TOP_APLL2_SEL		88
+#define CLK_TOP_I2S0_MCK_SEL		89
+#define CLK_TOP_I2S1_MCK_SEL		90
+#define CLK_TOP_I2S2_MCK_SEL		91
+#define CLK_TOP_I2S3_MCK_SEL		92
+#define CLK_TOP_APLL1_DIV		93
+#define CLK_TOP_APLL2_DIV		94
+#define CLK_TOP_I2S0_MCK_DIV		95
+#define CLK_TOP_I2S1_MCK_DIV		96
+#define CLK_TOP_I2S2_MCK_DIV		97
+#define CLK_TOP_I2S3_MCK_DIV		98
+#define CLK_TOP_A1SYS_HP_DIV		99
+#define CLK_TOP_A2SYS_HP_DIV		100
+#define CLK_TOP_APLL1_DIV_PD		101
+#define CLK_TOP_APLL2_DIV_PD		102
+#define CLK_TOP_I2S0_MCK_DIV_PD		103
+#define CLK_TOP_I2S1_MCK_DIV_PD		104
+#define CLK_TOP_I2S2_MCK_DIV_PD		105
+#define CLK_TOP_I2S3_MCK_DIV_PD		106
+
+/* INFRACFG */
+
+#define CLK_INFRA_DBGCLK_PD		0
+#define CLK_INFRA_TRNG			1
+#define CLK_INFRA_AUDIO_PD		2
+#define CLK_INFRA_IRRX_PD		3
+#define CLK_INFRA_APXGPT_PD		4
+#define CLK_INFRA_PMIC_PD		5
+
+/* PERICFG */
+
+#define CLK_PERI_THERM_PD		0
+#define CLK_PERI_PWM1_PD		1
+#define CLK_PERI_PWM2_PD		2
+#define CLK_PERI_PWM3_PD		3
+#define CLK_PERI_PWM4_PD		4
+#define CLK_PERI_PWM5_PD		5
+#define CLK_PERI_PWM6_PD		6
+#define CLK_PERI_PWM7_PD		7
+#define CLK_PERI_PWM_PD			8
+#define CLK_PERI_AP_DMA_PD		9
+#define CLK_PERI_MSDC30_0_PD		10
+#define CLK_PERI_MSDC30_1_PD		11
+#define CLK_PERI_UART0_PD		12
+#define CLK_PERI_UART1_PD		13
+#define CLK_PERI_UART2_PD		14
+#define CLK_PERI_UART3_PD		15
+#define CLK_PERI_BTIF_PD		16
+#define CLK_PERI_I2C0_PD		17
+#define CLK_PERI_I2C1_PD		18
+#define CLK_PERI_I2C2_PD		19
+#define CLK_PERI_SPI1_PD		20
+#define CLK_PERI_AUXADC_PD		21
+#define CLK_PERI_SPI0_PD		22
+#define CLK_PERI_SNFI_PD		23
+#define CLK_PERI_NFI_PD			24
+#define CLK_PERI_NFIECC_PD		25
+#define CLK_PERI_FLASH_PD		26
+#define CLK_PERI_IRTX_PD		27
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIV2PLL		2
+#define CLK_APMIXED_ETH1PLL		3
+#define CLK_APMIXED_ETH2PLL		4
+#define CLK_APMIXED_AUD1PLL		5
+#define CLK_APMIXED_AUD2PLL		6
+#define CLK_APMIXED_TRGPLL		7
+#define CLK_APMIXED_SGMIPLL		8
+
+/* AUDIOSYS */
+
+#define CLK_AUDIO_AFE			0
+#define CLK_AUDIO_HDMI			1
+#define CLK_AUDIO_SPDF			2
+#define CLK_AUDIO_APLL			3
+#define CLK_AUDIO_I2SIN1		4
+#define CLK_AUDIO_I2SIN2		5
+#define CLK_AUDIO_I2SIN3		6
+#define CLK_AUDIO_I2SIN4		7
+#define CLK_AUDIO_I2SO1			8
+#define CLK_AUDIO_I2SO2			9
+#define CLK_AUDIO_I2SO3			10
+#define CLK_AUDIO_I2SO4			11
+#define CLK_AUDIO_ASRCI1		12
+#define CLK_AUDIO_ASRCI2		13
+#define CLK_AUDIO_ASRCO1		14
+#define CLK_AUDIO_ASRCO2		15
+#define CLK_AUDIO_INTDIR		16
+#define CLK_AUDIO_A1SYS			17
+#define CLK_AUDIO_A2SYS			18
+#define CLK_AUDIO_UL1			19
+#define CLK_AUDIO_UL2			20
+#define CLK_AUDIO_UL3			21
+#define CLK_AUDIO_UL4			22
+#define CLK_AUDIO_UL5			23
+#define CLK_AUDIO_UL6			24
+#define CLK_AUDIO_DL1			25
+#define CLK_AUDIO_DL2			26
+#define CLK_AUDIO_DL3			27
+#define CLK_AUDIO_DL4			28
+#define CLK_AUDIO_DL5			29
+#define CLK_AUDIO_DL6			30
+#define CLK_AUDIO_DLMCH			31
+#define CLK_AUDIO_ARB1			32
+#define CLK_AUDIO_AWB			33
+#define CLK_AUDIO_AWB3			34
+#define CLK_AUDIO_DAI			35
+#define CLK_AUDIO_MOD			36
+#define CLK_AUDIO_ASRCI3		37
+#define CLK_AUDIO_ASRCI4		38
+#define CLK_AUDIO_ASRCO3		39
+#define CLK_AUDIO_ASRCO4		40
+#define CLK_AUDIO_MEM_ASRC1		41
+#define CLK_AUDIO_MEM_ASRC2		42
+#define CLK_AUDIO_MEM_ASRC3		43
+#define CLK_AUDIO_MEM_ASRC4		44
+#define CLK_AUDIO_MEM_ASRC5		45
+#define CLK_AUDIO_AFE_CONN		46
+#define CLK_AUDIO_NR_CLK		47
+
+/* SSUSBSYS */
+
+#define CLK_SSUSB_U2_PHY_1P_EN		0
+#define CLK_SSUSB_U2_PHY_EN		1
+#define CLK_SSUSB_REF_EN		2
+#define CLK_SSUSB_SYS_EN		3
+#define CLK_SSUSB_MCU_EN		4
+#define CLK_SSUSB_DMA_EN		5
+#define CLK_SSUSB_NR_CLK		6
+
+/* PCIESYS */
+
+#define CLK_PCIE_P1_AUX_EN		0
+#define CLK_PCIE_P1_OBFF_EN		1
+#define CLK_PCIE_P1_AHB_EN		2
+#define CLK_PCIE_P1_AXI_EN		3
+#define CLK_PCIE_P1_MAC_EN		4
+#define CLK_PCIE_P1_PIPE_EN		5
+#define CLK_PCIE_P0_AUX_EN		6
+#define CLK_PCIE_P0_OBFF_EN		7
+#define CLK_PCIE_P0_AHB_EN		8
+#define CLK_PCIE_P0_AXI_EN		9
+#define CLK_PCIE_P0_MAC_EN		10
+#define CLK_PCIE_P0_PIPE_EN		11
+#define CLK_SATA_AHB_EN			12
+#define CLK_SATA_AXI_EN			13
+#define CLK_SATA_ASIC_EN		14
+#define CLK_SATA_RBC_EN			15
+#define CLK_SATA_PM_EN			16
+#define CLK_PCIE_NR_CLK			17
+
+/* ETHSYS */
+
+#define CLK_ETH_HSDMA_EN		0
+#define CLK_ETH_ESW_EN			1
+#define CLK_ETH_GP2_EN			2
+#define CLK_ETH_GP1_EN			3
+#define CLK_ETH_GP0_EN			4
+
+/* SGMIISYS */
+
+#define CLK_SGMII_TX250M_EN		0
+#define CLK_SGMII_RX250M_EN		1
+#define CLK_SGMII_CDR_REF		2
+#define CLK_SGMII_CDR_FB		3
+
+#endif /* _DT_BINDINGS_CLK_MT7622_H */
+
diff --git a/include/dt-bindings/clock/mt8512-clk.h b/include/dt-bindings/clock/mt8512-clk.h
new file mode 100644
index 0000000000..fdc3474c01
--- /dev/null
+++ b/include/dt-bindings/clock/mt8512-clk.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8512_H
+#define _DT_BINDINGS_CLK_MT8512_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL		0
+#define CLK_TOP_CLK32K			1
+#define CLK_TOP_SYSPLL1_D2		2
+#define CLK_TOP_SYSPLL1_D4		3
+#define CLK_TOP_SYSPLL1_D8		4
+#define CLK_TOP_SYSPLL1_D16		5
+#define CLK_TOP_SYSPLL_D3		6
+#define CLK_TOP_SYSPLL2_D2		7
+#define CLK_TOP_SYSPLL2_D4		8
+#define CLK_TOP_SYSPLL2_D8		9
+#define CLK_TOP_SYSPLL_D5		10
+#define CLK_TOP_SYSPLL3_D4		11
+#define CLK_TOP_SYSPLL_D7		12
+#define CLK_TOP_SYSPLL4_D2		13
+#define CLK_TOP_UNIVPLL			14
+#define CLK_TOP_UNIVPLL_D2		15
+#define CLK_TOP_UNIVPLL1_D2		16
+#define CLK_TOP_UNIVPLL1_D4		17
+#define CLK_TOP_UNIVPLL1_D8		18
+#define CLK_TOP_UNIVPLL_D3		19
+#define CLK_TOP_UNIVPLL2_D2		20
+#define CLK_TOP_UNIVPLL2_D4		21
+#define CLK_TOP_UNIVPLL2_D8		22
+#define CLK_TOP_UNIVPLL_D5		23
+#define CLK_TOP_UNIVPLL3_D2		24
+#define CLK_TOP_UNIVPLL3_D4		25
+#define CLK_TOP_TCONPLL_D2		26
+#define CLK_TOP_TCONPLL_D4		27
+#define CLK_TOP_TCONPLL_D8		28
+#define CLK_TOP_TCONPLL_D16		29
+#define CLK_TOP_TCONPLL_D32		30
+#define CLK_TOP_TCONPLL_D64		31
+#define CLK_TOP_USB20_192M		32
+#define CLK_TOP_USB20_192M_D2		33
+#define CLK_TOP_USB20_192M_D4_T		34
+#define CLK_TOP_APLL1			35
+#define CLK_TOP_APLL1_D2		36
+#define CLK_TOP_APLL1_D3		37
+#define CLK_TOP_APLL1_D4		38
+#define CLK_TOP_APLL1_D8		39
+#define CLK_TOP_APLL1_D16		40
+#define CLK_TOP_APLL2			41
+#define CLK_TOP_APLL2_D2		42
+#define CLK_TOP_APLL2_D3		43
+#define CLK_TOP_APLL2_D4		44
+#define CLK_TOP_APLL2_D8		45
+#define CLK_TOP_APLL2_D16		46
+#define CLK_TOP_CLK26M			47
+#define CLK_TOP_SYS_26M_D2		48
+#define CLK_TOP_MSDCPLL			49
+#define CLK_TOP_MSDCPLL_D2		50
+#define CLK_TOP_DSPPLL			51
+#define CLK_TOP_DSPPLL_D2		52
+#define CLK_TOP_DSPPLL_D4		53
+#define CLK_TOP_DSPPLL_D8		54
+#define CLK_TOP_IPPLL			55
+#define CLK_TOP_IPPLL_D2		56
+#define CLK_TOP_NFI2X_CK_D2		57
+#define CLK_TOP_AXI_SEL			58
+#define CLK_TOP_MEM_SEL			59
+#define CLK_TOP_UART_SEL		60
+#define CLK_TOP_SPI_SEL			61
+#define CLK_TOP_SPIS_SEL		62
+#define CLK_TOP_MSDC50_0_HC_SEL		63
+#define CLK_TOP_MSDC2_2_HC_SEL		64
+#define CLK_TOP_MSDC50_0_SEL		65
+#define CLK_TOP_MSDC50_2_SEL		66
+#define CLK_TOP_MSDC30_1_SEL		67
+#define CLK_TOP_AUDIO_SEL		68
+#define CLK_TOP_AUD_INTBUS_SEL		69
+#define CLK_TOP_HAPLL1_SEL		70
+#define CLK_TOP_HAPLL2_SEL		71
+#define CLK_TOP_A2SYS_SEL		72
+#define CLK_TOP_A1SYS_SEL		73
+#define CLK_TOP_ASM_L_SEL		74
+#define CLK_TOP_ASM_M_SEL		75
+#define CLK_TOP_ASM_H_SEL		76
+#define CLK_TOP_AUD_SPDIF_SEL		77
+#define CLK_TOP_AUD_1_SEL		78
+#define CLK_TOP_AUD_2_SEL		79
+#define CLK_TOP_SSUSB_SYS_SEL		80
+#define CLK_TOP_SSUSB_XHCI_SEL		81
+#define CLK_TOP_SPM_SEL			82
+#define CLK_TOP_I2C_SEL			83
+#define CLK_TOP_PWM_SEL			84
+#define CLK_TOP_DSP_SEL			85
+#define CLK_TOP_NFI2X_SEL		86
+#define CLK_TOP_SPINFI_SEL		87
+#define CLK_TOP_ECC_SEL			88
+#define CLK_TOP_GCPU_SEL		89
+#define CLK_TOP_GCPU_CPM_SEL		90
+#define CLK_TOP_MBIST_DIAG_SEL		91
+#define CLK_TOP_IP0_NNA_SEL		92
+#define CLK_TOP_IP1_NNA_SEL		93
+#define CLK_TOP_IP2_WFST_SEL		94
+#define CLK_TOP_SFLASH_SEL		95
+#define CLK_TOP_SRAM_SEL		96
+#define CLK_TOP_MM_SEL			97
+#define CLK_TOP_DPI0_SEL		98
+#define CLK_TOP_DBG_ATCLK_SEL		99
+#define CLK_TOP_OCC_104M_SEL		100
+#define CLK_TOP_OCC_68M_SEL		101
+#define CLK_TOP_OCC_182M_SEL		102
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_CONN_32K		0
+#define CLK_TOP_CONN_26M		1
+#define CLK_TOP_DSP_32K			2
+#define CLK_TOP_DSP_26M			3
+#define CLK_TOP_USB20_48M_EN		4
+#define CLK_TOP_UNIVPLL_48M_EN		5
+#define CLK_TOP_SSUSB_TOP_CK_EN		6
+#define CLK_TOP_SSUSB_PHY_CK_EN		7
+#define CLK_TOP_I2SI1_MCK		8
+#define CLK_TOP_TDMIN_MCK		9
+#define CLK_TOP_I2SO1_MCK		10
+
+/* INFRASYS */
+
+#define CLK_INFRA_DSP_AXI		0
+#define CLK_INFRA_APXGPT		1
+#define CLK_INFRA_ICUSB			2
+#define CLK_INFRA_GCE			3
+#define CLK_INFRA_THERM			4
+#define CLK_INFRA_PWM_HCLK		5
+#define CLK_INFRA_PWM1			6
+#define CLK_INFRA_PWM2			7
+#define CLK_INFRA_PWM3			8
+#define CLK_INFRA_PWM4			9
+#define CLK_INFRA_PWM5			10
+#define CLK_INFRA_PWM			11
+#define CLK_INFRA_UART0			12
+#define CLK_INFRA_UART1			13
+#define CLK_INFRA_UART2			14
+#define CLK_INFRA_DSP_UART		15
+#define CLK_INFRA_GCE_26M		16
+#define CLK_INFRA_CQDMA_FPC		17
+#define CLK_INFRA_BTIF			18
+#define CLK_INFRA_SPI			19
+#define CLK_INFRA_MSDC0			20
+#define CLK_INFRA_MSDC1			21
+#define CLK_INFRA_DVFSRC		22
+#define CLK_INFRA_GCPU			23
+#define CLK_INFRA_TRNG			24
+#define CLK_INFRA_AUXADC		25
+#define CLK_INFRA_AUXADC_MD		26
+#define CLK_INFRA_AP_DMA		27
+#define CLK_INFRA_DEBUGSYS		28
+#define CLK_INFRA_AUDIO			29
+#define CLK_INFRA_FLASHIF		30
+#define CLK_INFRA_PWM_FB6		31
+#define CLK_INFRA_PWM_FB7		32
+#define CLK_INFRA_AUD_ASRC		33
+#define CLK_INFRA_AUD_26M		34
+#define CLK_INFRA_SPIS			35
+#define CLK_INFRA_CQ_DMA		36
+#define CLK_INFRA_AP_MSDC0		37
+#define CLK_INFRA_MD_MSDC0		38
+#define CLK_INFRA_MSDC0_SRC		39
+#define CLK_INFRA_MSDC1_SRC		40
+#define CLK_INFRA_IRRX_26M		41
+#define CLK_INFRA_IRRX_32K		42
+#define CLK_INFRA_I2C0_AXI		43
+#define CLK_INFRA_I2C1_AXI		44
+#define CLK_INFRA_I2C2_AXI		45
+#define CLK_INFRA_NFI			46
+#define CLK_INFRA_NFIECC		47
+#define CLK_INFRA_NFI_HCLK		48
+#define CLK_INFRA_SUSB_133		49
+#define CLK_INFRA_USB_SYS		50
+#define CLK_INFRA_USB_XHCI		51
+#define CLK_INFRA_NR_CLK		52
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIVPLL2		2
+#define CLK_APMIXED_MSDCPLL		3
+#define CLK_APMIXED_APLL1		4
+#define CLK_APMIXED_APLL2		5
+#define CLK_APMIXED_IPPLL		6
+#define CLK_APMIXED_DSPPLL		7
+#define CLK_APMIXED_TCONPLL		8
+#define CLK_APMIXED_NR_CLK		9
+
+#endif /* _DT_BINDINGS_CLK_MT8512_H */